From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36639) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbEj9-0006Ue-Gl for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:13:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VbEj3-0007sJ-BP for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:13:19 -0400 Received: from www11.your-server.de ([213.133.104.11]:33130) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbEj3-0007sE-5Z for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:13:13 -0400 From: Sebastian Macke Date: Tue, 29 Oct 2013 20:04:54 +0100 Message-Id: <1383073495-5332-13-git-send-email-sebastian@macke.de> In-Reply-To: <1383073495-5332-1-git-send-email-sebastian@macke.de> References: <1383073495-5332-1-git-send-email-sebastian@macke.de> Subject: [Qemu-devel] [PATCH 12/13] target-openrisc: Add correct gdb information for the pc value List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, proljc@gmail.com Cc: Sebastian Macke , openrisc@lists.openrisc.net, openrisc@lists.opencores.org The former patch which removed npc and ppc also removed the part in which the registers were send to gdb. But the npc parameter is necessary and the numbering of registers is fixed within gdb. The correct npc value is the current pc value. Signed-off-by: Sebastian Macke --- target-openrisc/gdbstub.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c index c1f9561..81f0f43 100644 --- a/target-openrisc/gdbstub.c +++ b/target-openrisc/gdbstub.c @@ -31,7 +31,13 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) } else { switch (n) { - case 32: /* SR */ + case 32: /* PPC */ + return gdb_get_reg32(mem_buf, env->pc-4); + + case 33: /* NPC */ + return gdb_get_reg32(mem_buf, env->pc); + + case 34: /* SR */ return gdb_get_reg32(mem_buf, ENV_GET_SR(env)); default: @@ -59,10 +65,14 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } else { switch (n) { - case 32: /* SR */ + case 33: /* NPC */ + env->pc = tmp; + + case 34: /* SR */ ENV_SET_SR(env, tmp); break; + case 32: /* PPC is not allowed to write */ default: break; } -- 1.8.4.1