From: Sebastian Macke <sebastian@macke.de>
To: qemu-devel@nongnu.org, proljc@gmail.com
Cc: Sebastian Macke <sebastian@macke.de>,
openrisc@lists.openrisc.net, openrisc@lists.opencores.org
Subject: [Qemu-devel] [PATCH 03/13] target-openrisc: Separate of load/store instructions
Date: Tue, 29 Oct 2013 20:04:45 +0100 [thread overview]
Message-ID: <1383073495-5332-4-git-send-email-sebastian@macke.de> (raw)
In-Reply-To: <1383073495-5332-1-git-send-email-sebastian@macke.de>
This patch separates the load and store instruction to a
separate function.
The repetition of the source code can be reduced and further
optimizations can be implemented.
In this case it checks for a zero offset and optimizes it.
Additional this patch solves a severe bug for the softmmu emulation.
The pc has to be saved as these instructions can fail and lead
to a tlb miss exception.
Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
target-openrisc/translate.c | 130 ++++++++++++++++++++++++++------------------
1 file changed, 76 insertions(+), 54 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 31f8717..1bb686c 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -692,6 +692,73 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
}
}
+static void gen_loadstore(DisasContext *dc, uint32 op0,
+ uint32_t ra, uint32_t rb, uint32_t rd,
+ uint32_t offset)
+{
+
+/* The load and store instructions can fail and lead to a
+ * tlb miss exception. The correct pc has to be stored for
+ * this case.
+ */
+#if !defined(CONFIG_USER_ONLY)
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
+#endif
+
+ TCGv t0 = cpu_R[ra];
+ if (offset != 0) {
+ t0 = tcg_temp_new();
+ tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(offset, 16));
+ }
+
+ switch (op0) {
+ case 0x21: /* l.lwz */
+ tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc->mem_idx);
+ break;
+
+ case 0x22: /* l.lws */
+ tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc->mem_idx);
+ break;
+
+ case 0x23: /* l.lbz */
+ tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc->mem_idx);
+ break;
+
+ case 0x24: /* l.lbs */
+ tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc->mem_idx);
+ break;
+
+ case 0x25: /* l.lhz */
+ tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc->mem_idx);
+ break;
+
+ case 0x26: /* l.lhs */
+ tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc->mem_idx);
+ break;
+
+ case 0x35: /* l.sw */
+ tcg_gen_qemu_st32(cpu_R[rb], t0, dc->mem_idx);
+ break;
+
+ case 0x36: /* l.sb */
+ tcg_gen_qemu_st8(cpu_R[rb], t0, dc->mem_idx);
+ break;
+
+ case 0x37: /* l.sh */
+ tcg_gen_qemu_st16(cpu_R[rb], t0, dc->mem_idx);
+ break;
+
+ default:
+ break;
+ }
+
+ if (offset != 0) {
+ tcg_temp_free(t0);
+ }
+
+}
+
+
static void dec_misc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1;
@@ -843,62 +910,32 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
case 0x21: /* l.lwz */
LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
+ gen_loadstore(dc, op0, ra, rb, rd, I16);
break;
case 0x22: /* l.lws */
LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
+ gen_loadstore(dc, op0, ra, rb, rd, I16);
break;
case 0x23: /* l.lbz */
LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
+ gen_loadstore(dc, op0, ra, rb, rd, I16);
break;
case 0x24: /* l.lbs */
LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
+ gen_loadstore(dc, op0, ra, rb, rd, I16);
break;
case 0x25: /* l.lhz */
LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
+ gen_loadstore(dc, op0, ra, rb, rd, I16);
break;
case 0x26: /* l.lhs */
LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
+ gen_loadstore(dc, op0, ra, rb, rd, I16);
break;
case 0x27: /* l.addi */
@@ -1047,32 +1084,17 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
case 0x35: /* l.sw */
LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
- tcg_gen_qemu_st32(cpu_R[rb], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
+ gen_loadstore(dc, op0, ra, rb, rd, tmp);
break;
case 0x36: /* l.sb */
LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
- tcg_gen_qemu_st8(cpu_R[rb], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
+ gen_loadstore(dc, op0, ra, rb, rd, tmp);
break;
case 0x37: /* l.sh */
+ gen_loadstore(dc, op0, ra, rb, rd, tmp);
LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
- tcg_gen_qemu_st16(cpu_R[rb], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
break;
default:
--
1.8.4.1
next prev parent reply other threads:[~2013-10-29 19:05 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-29 19:04 [Qemu-devel] [PATCH 00/13] target-openrisc: More optimizations and corrections Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 01/13] target-openrisc: Implement translation block chaining Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 02/13] target-openrisc: Separate Delayed slot handling from main loop Sebastian Macke
2013-10-29 19:04 ` Sebastian Macke [this message]
2013-10-29 20:05 ` [Qemu-devel] [PATCH 03/13] target-openrisc: Separate of load/store instructions Max Filippov
2013-10-29 21:36 ` Sebastian Macke
2013-10-29 21:49 ` Richard Henderson
2013-10-29 22:55 ` Max Filippov
2013-10-29 23:37 ` Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 04/13] target-openrisc: sync flags only when necessary Sebastian Macke
2013-10-29 21:51 ` Richard Henderson
2013-10-29 19:04 ` [Qemu-devel] [PATCH 05/13] target-openrisc: Remove TLB flush on exception Sebastian Macke
2013-10-29 19:47 ` Peter Maydell
2013-10-29 22:41 ` Sebastian Macke
2013-11-01 18:58 ` Peter Maydell
2013-11-02 1:21 ` Richard Henderson
2013-11-06 22:59 ` [Qemu-devel] [Openrisc] " Edgar E. Iglesias
2013-11-02 1:29 ` [Qemu-devel] " Richard Henderson
2013-10-29 19:04 ` [Qemu-devel] [PATCH 06/13] target-openrisc: Remove TLB flush from l.rfe instruction Sebastian Macke
2013-10-29 21:01 ` Max Filippov
2013-10-29 21:53 ` Sebastian Macke
2013-10-29 22:20 ` Max Filippov
2013-10-29 23:14 ` Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 07/13] target-openrisc: Correct l.cmov conditional check Sebastian Macke
2013-10-29 21:15 ` Max Filippov
2013-10-29 21:23 ` Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 08/13] target-openrisc: Test for Overflow exception statically Sebastian Macke
2013-10-29 21:25 ` Max Filippov
2013-10-29 22:06 ` Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 09/13] target-openrisc: Add CPU which neglects Carry and Overflow Flag Sebastian Macke
2013-10-30 18:14 ` Richard Henderson
2013-10-30 19:22 ` Sebastian Macke
2013-10-30 19:31 ` Richard Henderson
2013-10-29 19:04 ` [Qemu-devel] [PATCH 10/13] target-openrisc: Correct target number for 64 bit llseek Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 11/13] target-openrisc: use jmp_pc as flag variable for branches Sebastian Macke
2013-10-30 18:33 ` Richard Henderson
2013-10-30 19:07 ` Sebastian Macke
2013-10-30 19:32 ` Richard Henderson
2013-10-30 19:47 ` Richard Henderson
2013-10-30 21:08 ` Sebastian Macke
2013-10-30 22:02 ` Richard Henderson
2013-10-31 0:29 ` Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 12/13] target-openrisc: Add correct gdb information for the pc value Sebastian Macke
2013-10-29 19:04 ` [Qemu-devel] [PATCH 13/13] target-openrisc: Add In-circuit emulator support Sebastian Macke
2013-10-29 19:53 ` [Qemu-devel] [PATCH 00/13] target-openrisc: More optimizations and corrections Peter Maydell
2013-10-29 21:15 ` Max Filippov
2013-10-29 21:22 ` Sebastian Macke
2013-10-31 11:47 ` Jia Liu
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