From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34098) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbEbh-0003uP-05 for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:05:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VbEbW-0005QE-2c for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:05:36 -0400 Received: from www11.your-server.de ([213.133.104.11]:59988) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbEbV-0005QA-SJ for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:05:25 -0400 From: Sebastian Macke Date: Tue, 29 Oct 2013 20:04:47 +0100 Message-Id: <1383073495-5332-6-git-send-email-sebastian@macke.de> In-Reply-To: <1383073495-5332-1-git-send-email-sebastian@macke.de> References: <1383073495-5332-1-git-send-email-sebastian@macke.de> Subject: [Qemu-devel] [PATCH 05/13] target-openrisc: Remove TLB flush on exception List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, proljc@gmail.com Cc: Sebastian Macke , openrisc@lists.openrisc.net, openrisc@lists.opencores.org The TLB flush is not necessary as the mmu_index field already takes care of correct memory locations. Instead the tb flag field must be expanded that the exception takes the correct translation block. Signed-off-by: Sebastian Macke --- target-openrisc/cpu.h | 4 ++-- target-openrisc/interrupt.c | 4 ---- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 24afe6f..057821d 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -85,7 +85,7 @@ enum { #define SPR_VR 0xFFFF003F /* Internal flags, delay slot flag */ -#define D_FLAG 1 +#define D_FLAG 2 /* Interrupt */ #define NR_IRQS 32 @@ -412,7 +412,7 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, *pc = env->pc; *cs_base = 0; /* D_FLAG -- branch instruction exception */ - *flags = (env->flags & D_FLAG); + *flags = (env->flags & D_FLAG) | (env->sr & SR_SM); } static inline int cpu_mmu_index(CPUOpenRISCState *env) diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index d1d6ae2..ee98ed3 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -41,10 +41,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->epcr += 4; } - /* For machine-state changed between user-mode and supervisor mode, - we need flush TLB when we enter&exit EXCP. */ - tlb_flush(env, 1); - env->esr = ENV_GET_SR(env); env->sr &= ~SR_DME; env->sr &= ~SR_IME; -- 1.8.4.1