From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53248) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbylR-00034P-A1 for qemu-devel@nongnu.org; Thu, 31 Oct 2013 16:22:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VbylI-0000TY-SQ for qemu-devel@nongnu.org; Thu, 31 Oct 2013 16:22:45 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:34607) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbylI-0000TP-HD for qemu-devel@nongnu.org; Thu, 31 Oct 2013 16:22:36 -0400 Received: by mail-pa0-f42.google.com with SMTP id kp14so3065484pab.29 for ; Thu, 31 Oct 2013 13:22:35 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 31 Oct 2013 13:22:05 -0700 Message-Id: <1383250929-10288-17-git-send-email-rth@twiddle.net> In-Reply-To: <1383250929-10288-1-git-send-email-rth@twiddle.net> References: <1383250929-10288-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 16/20] tcg-ia64: Move tlb addend load into tlb read List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@amazon.com, aurelien@aurel32.net Signed-off-by: Richard Henderson --- tcg/ia64/tcg-target.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c index 985e213..b62337e 100644 --- a/tcg/ia64/tcg-target.c +++ b/tcg/ia64/tcg-target.c @@ -1563,7 +1563,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) > 0x1fffff) /* Load and compare a TLB entry, and return the result in (p6, p7). - R2 is loaded with the address of the addend TLB entry. + R2 is loaded with the addend TLB entry. R57 is loaded with the address, zero extented on 32-bit targets. R1, R3 are clobbered, leaving R56 free for... BSWAP_1, BSWAP_2 and I-slot insns for swapping data for store. */ @@ -1619,7 +1619,7 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGReg addr_reg, TCG_REG_R2, off_add - off_rw), bswap1); tcg_out_bundle(s, mmI, - INSN_NOP_M, + tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, TCG_REG_R2), tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6, TCG_REG_P7, TCG_REG_R1, TCG_REG_R3), bswap2); @@ -1662,30 +1662,30 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, (tcg_target_long) qemu_ld_helpers[s_bits])); tcg_out_bundle(s, MmI, - tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, + tcg_opc_m3 (TCG_REG_P7, OPC_LD8_M3, TCG_REG_R3, TCG_REG_R2, 8), - tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, - TCG_REG_R3, TCG_REG_R57), + tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R2, + TCG_REG_R2, TCG_REG_R57), tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, TCG_REG_R3, 0)); if (bswap && s_bits == MO_16) { tcg_out_bundle(s, MmI, tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], - TCG_REG_R8, TCG_REG_R3), + TCG_REG_R8, TCG_REG_R2), tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, TCG_REG_R8, TCG_REG_R8, 15, 15)); } else if (bswap && s_bits == MO_32) { tcg_out_bundle(s, MmI, tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], - TCG_REG_R8, TCG_REG_R3), + TCG_REG_R8, TCG_REG_R2), tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, TCG_REG_R8, TCG_REG_R8, 31, 31)); } else { tcg_out_bundle(s, mmI, tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], - TCG_REG_R8, TCG_REG_R3), + TCG_REG_R8, TCG_REG_R2), tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), INSN_NOP_I); } @@ -1757,10 +1757,10 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, (tcg_target_long) qemu_st_helpers[s_bits])); tcg_out_bundle(s, MmI, - tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, + tcg_opc_m3 (TCG_REG_P7, OPC_LD8_M3, TCG_REG_R3, TCG_REG_R2, 8), - tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, - TCG_REG_R3, TCG_REG_R57), + tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R2, + TCG_REG_R2, TCG_REG_R57), tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, TCG_REG_R3, 0)); tcg_out_bundle(s, mii, @@ -1770,7 +1770,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, INSN_NOP_I); tcg_out_bundle(s, miB, tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits], - store_reg, TCG_REG_R3), + store_reg, TCG_REG_R2), tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R59, mem_index), tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, TCG_REG_B0, TCG_REG_B6)); -- 1.8.3.1