From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbylD-0002iT-JS for qemu-devel@nongnu.org; Thu, 31 Oct 2013 16:22:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vbyl6-0000Q2-4D for qemu-devel@nongnu.org; Thu, 31 Oct 2013 16:22:31 -0400 Received: from mail-pb0-x233.google.com ([2607:f8b0:400e:c01::233]:38314) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vbyl5-0000Pi-UD for qemu-devel@nongnu.org; Thu, 31 Oct 2013 16:22:24 -0400 Received: by mail-pb0-f51.google.com with SMTP id xa12so256096pbc.38 for ; Thu, 31 Oct 2013 13:22:23 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 31 Oct 2013 13:21:56 -0700 Message-Id: <1383250929-10288-8-git-send-email-rth@twiddle.net> In-Reply-To: <1383250929-10288-1-git-send-email-rth@twiddle.net> References: <1383250929-10288-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 07/20] tcg-ia64: Use ADDS for small addition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@amazon.com, aurelien@aurel32.net Avoids a wasted cycle loading up small constants. Simplify the code assuming the tcg optimizer is going to work and don't expect the first operand of the add to be constant. Signed-off-by: Richard Henderson --- tcg/ia64/tcg-target.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c index b7f74a9..be74606 100644 --- a/tcg/ia64/tcg-target.c +++ b/tcg/ia64/tcg-target.c @@ -1067,6 +1067,19 @@ static void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGReg ret, TCGArg arg1, tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2)); } +static inline void tcg_out_add(TCGContext *s, TCGReg ret, TCGReg arg1, + TCGArg arg2, int const_arg2) +{ + if (const_arg2 && arg2 == sextract64(arg2, 0, 14)) { + tcg_out_bundle(s, mmI, + INSN_NOP_M, + INSN_NOP_M, + tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, arg2, arg1)); + } else { + tcg_out_alu(s, OPC_ADD_A1, ret, arg1, 0, arg2, const_arg2); + } +} + static inline void tcg_out_eqv(TCGContext *s, TCGArg ret, TCGArg arg1, int const_arg1, TCGArg arg2, int const_arg2) @@ -2068,8 +2081,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_add_i32: case INDEX_op_add_i64: - tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1], - args[2], const_args[2]); + tcg_out_add(s, args[0], args[1], args[2], const_args[2]); break; case INDEX_op_sub_i32: case INDEX_op_sub_i64: @@ -2275,7 +2287,7 @@ static const TCGTargetOpDef ia64_op_defs[] = { { INDEX_op_st16_i32, { "rZ", "r" } }, { INDEX_op_st_i32, { "rZ", "r" } }, - { INDEX_op_add_i32, { "r", "rI", "rI" } }, + { INDEX_op_add_i32, { "r", "rZ", "rI" } }, { INDEX_op_sub_i32, { "r", "rI", "rI" } }, { INDEX_op_and_i32, { "r", "rI", "rI" } }, @@ -2322,7 +2334,7 @@ static const TCGTargetOpDef ia64_op_defs[] = { { INDEX_op_st32_i64, { "rZ", "r" } }, { INDEX_op_st_i64, { "rZ", "r" } }, - { INDEX_op_add_i64, { "r", "rI", "rI" } }, + { INDEX_op_add_i64, { "r", "rZ", "rI" } }, { INDEX_op_sub_i64, { "r", "rI", "rI" } }, { INDEX_op_and_i64, { "r", "rI", "rI" } }, -- 1.8.3.1