From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org, tommusta@gmail.com
Cc: qemu-ppc@nongnu.org
Subject: [Qemu-devel] [PATCH V3 08/13] Add VSX Vector Move Instructions
Date: Fri, 1 Nov 2013 08:21:18 -0500 [thread overview]
Message-ID: <1383312083-2536-9-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1383312083-2536-1-git-send-email-tommusta@gmail.com>
This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision
- xvnabsdp - Vector Negative Absolute Value Double-Precision
- xvnegdp - Vector Negate Double-Precision
- xvcpsgndp - Vector Copy Sign Double-Precision
- xvabssp - Vector Absolute Value Single-Precision
- xvnabssp - Vector Negative Absolute Value Single-Precision
- xvnegsp - Vector Negate Single-Precision
- xvcpsgnsp - Vector Copy Sign Single-Precision
V3: Per Paolo Bonzini's suggestion, used a temporary for the
sign mask and andc.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7409f77..e7d40a4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7215,6 +7215,69 @@ VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext * ctx) \
+ { \
+ TCGv_i64 xbh, xbl, sgm; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xbh = tcg_temp_new(); \
+ xbl = tcg_temp_new(); \
+ sgm = tcg_temp_new(); \
+ tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
+ tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
+ tcg_gen_movi_i64(sgm, sgn_mask); \
+ switch (op) { \
+ case OP_ABS: { \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_andc_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_NABS: { \
+ tcg_gen_or_i64(xbh, xbh, sgm); \
+ tcg_gen_or_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_NEG: { \
+ tcg_gen_xor_i64(xbh, xbh, sgm); \
+ tcg_gen_xor_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_CPSGN: { \
+ TCGv_i64 xah = tcg_temp_new(); \
+ TCGv_i64 xal = tcg_temp_new(); \
+ tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
+ tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
+ tcg_gen_and_i64(xah, xah, sgm); \
+ tcg_gen_and_i64(xal, xal, sgm); \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_andc_i64(xbl, xbl, sgm); \
+ tcg_gen_or_i64(xbh, xbh, xah); \
+ tcg_gen_or_i64(xbl, xbl, xal); \
+ tcg_temp_free(xah); \
+ tcg_temp_free(xal); \
+ break; \
+ } \
+ } \
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
+ tcg_temp_free(xbh); \
+ tcg_temp_free(xbl); \
+ tcg_temp_free(sgm); \
+ }
+
+VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+
+
/*** SPE extension ***/
/* Register moves */
@@ -9710,6 +9773,14 @@ GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
+GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
+GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
+GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
next prev parent reply other threads:[~2013-11-01 13:22 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-01 13:21 [Qemu-devel] [PATCH V3 00/13] Stage 2 VSX Support Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 01/13] Abandon GEN_VSX_* macros Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 02/13] Add lxsdx Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 03/13] Add lxvdsx Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 04/13] Add lxvw4x Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 05/13] Add stxsdx Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 06/13] Add stxvw4x Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 07/13] Add VSX Scalar Move Instructions Tom Musta
2013-11-01 13:21 ` Tom Musta [this message]
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 09/13] Add Power7 VSX Logical Instructions Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 10/13] Add xxmrgh/xxmrgl Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 11/13] Add xxsel Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 12/13] Add xxspltw Tom Musta
2013-11-01 13:21 ` [Qemu-devel] [PATCH V3 13/13] Add xxsldwi Tom Musta
2013-12-03 16:11 ` [Qemu-devel] [PATCH V3 00/13] Stage 2 VSX Support Tom Musta
2013-12-17 13:34 ` Alexander Graf
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