* [Qemu-devel] [PATCH for-1.7 0/3] sun4m: Add TCX FCode ROM and support for CG3 framebuffer
@ 2013-11-02 16:03 Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer Mark Cave-Ayland
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Mark Cave-Ayland @ 2013-11-02 16:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland, aliguori
(This is a repost of the complete patchset rebased and with for-1.7 in the
subject as requested by Anthony)
This patchset does two things: firstly it adds an FCode ROM for the existing
TCX framebuffer, and secondly provides QEMU with an implementation of the Sun
CG3 8-bit framebuffer. It is based upon Bob Breuer's original work which has
been rebased onto git master, and is now capable of running with the OpenBIOS
CG3 FCode ROM instead of requiring copies of proprietary Sun ROMs.
Note this patch has been around for a month or so but has been waiting for the
updated OpenBIOS images to be included in QEMU. The reason for adding the TCX
FCode ROM first is because Open Firmware such as OpenBIOS detects which
framebuffer is in use by "executing" the FCode in the ROM to create the node
in the device tree in exactly the same way as real hardware. This is in
contrast to older versions of OpenBIOS where everything was hardcoded to use
the TCX framebuffer.
While this patch has not received much review, it is a reasonably simple and
self-contained patchset and has been updated to reflect the comments received
from the initial post of the "Add FCode ROM for TCX framebuffer" patch. For
this reason, I feel that this patchset is a candidate for 1.7.
The motivation behind this patch is that older operating systems such as
Debian Woody and Solaris (running OpenWindows) do not contain drivers for the
TCX framebuffer and as a result currently cannot run in graphical mode. The
screenshots linked below show qemu-system-sparc successfully running both
Debian Woody and the Solaris 8 installer in graphical mode with the CG3
framebuffer selected during testing:
http://www.ilande.co.uk/tmp/debian-woody.png
http://www.ilande.co.uk/tmp/sol8-1.png
http://www.ilande.co.uk/tmp/sol8-2.png
The CG3 framebuffer is selected by passing -vga cg3 on the command line to
qemu-system-sparc. If either -vga tcx is specified (or the -vga argument is
omitted) then qemu-system-sparc defaults to using the existing TCX
framebuffer to maintain compatibility.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland (3):
sun4m: Add FCode ROM for TCX framebuffer
sun4m: Add Sun CG3 framebuffer and corresponding OpenBIOS FCode ROM
sun4m: Add Sun CG3 framebuffer initialisation function
Makefile | 2 +-
default-configs/sparc-softmmu.mak | 1 +
hw/display/Makefile.objs | 1 +
hw/display/cg3.c | 359 +++++++++++++++++++++++++++++++++++++
hw/display/tcx.c | 27 ++-
hw/sparc/sun4m.c | 77 +++++++-
include/sysemu/sysemu.h | 1 +
pc-bios/QEMU,cgthree.bin | Bin 0 -> 682 bytes
pc-bios/QEMU,tcx.bin | Bin 0 -> 1242 bytes
pc-bios/README | 4 +-
vl.c | 24 +++
11 files changed, 483 insertions(+), 13 deletions(-)
create mode 100644 hw/display/cg3.c
create mode 100644 pc-bios/QEMU,cgthree.bin
create mode 100644 pc-bios/QEMU,tcx.bin
--
1.7.10.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer
2013-11-02 16:03 [Qemu-devel] [PATCH for-1.7 0/3] sun4m: Add TCX FCode ROM and support for CG3 framebuffer Mark Cave-Ayland
@ 2013-11-02 16:03 ` Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 2/3] sun4m: Add Sun CG3 framebuffer and corresponding OpenBIOS FCode ROM Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 3/3] sun4m: Add Sun CG3 framebuffer initialisation function Mark Cave-Ayland
2 siblings, 0 replies; 7+ messages in thread
From: Mark Cave-Ayland @ 2013-11-02 16:03 UTC (permalink / raw)
To: qemu-devel
Cc: Blue Swirl, Bob Breuer, Mark Cave-Ayland, Artyom Tarasenko,
aliguori
Upstream OpenBIOS now implements SBus probing in order to determine the
contents of a physical bus slot, which is required to allow OpenBIOS to
identify the framebuffer without help from the fw_cfg interface.
SBus probing works by detecting the presence of an FCode program
(effectively tokenised Forth) at the base address of each slot, and if
present executes it so that it creates its own device node in the
OpenBIOS device tree.
The FCode ROM is generated as part of the OpenBIOS build and should
generally be updated at the same time.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Blue Swirl <blauwirbel@gmail.com>
CC: Bob Breuer <breuerr@mc.net>
CC: Artyom Tarasenko <atar4qemu@gmail.com>
---
Makefile | 2 +-
hw/display/tcx.c | 27 ++++++++++++++++++++++++++-
hw/sparc/sun4m.c | 17 ++++++++++-------
pc-bios/QEMU,tcx.bin | Bin 0 -> 1242 bytes
pc-bios/README | 4 ++--
5 files changed, 39 insertions(+), 11 deletions(-)
create mode 100644 pc-bios/QEMU,tcx.bin
diff --git a/Makefile b/Makefile
index b15003f..3235039 100644
--- a/Makefile
+++ b/Makefile
@@ -286,7 +286,7 @@ ifdef INSTALL_BLOBS
BLOBS=bios.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin \
acpi-dsdt.aml q35-acpi-dsdt.aml \
-ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc \
+ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin \
pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \
pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \
efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index 24876d3..06bf66f 100644
--- a/hw/display/tcx.c
+++ b/hw/display/tcx.c
@@ -25,8 +25,12 @@
#include "qemu-common.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
+#include "hw/loader.h"
#include "hw/sysbus.h"
+#define TCX_ROM_FILE "QEMU,tcx.bin"
+#define FCODE_MAX_ROM_SIZE 0x10000
+
#define MAXX 1024
#define MAXY 768
#define TCX_DAC_NREGS 16
@@ -43,6 +47,8 @@ typedef struct TCXState {
QemuConsole *con;
uint8_t *vram;
uint32_t *vram24, *cplane;
+ hwaddr prom_addr;
+ MemoryRegion rom;
MemoryRegion vram_mem;
MemoryRegion vram_8bit;
MemoryRegion vram_24bit;
@@ -529,14 +535,32 @@ static int tcx_init1(SysBusDevice *dev)
{
TCXState *s = TCX(dev);
ram_addr_t vram_offset = 0;
- int size;
+ int size, ret;
uint8_t *vram_base;
+ char *fcode_filename;
memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram",
s->vram_size * (1 + 4 + 4));
vmstate_register_ram_global(&s->vram_mem);
vram_base = memory_region_get_ram_ptr(&s->vram_mem);
+ /* FCode ROM */
+ memory_region_init_ram(&s->rom, NULL, "tcx.prom", FCODE_MAX_ROM_SIZE);
+ vmstate_register_ram_global(&s->rom);
+ memory_region_set_readonly(&s->rom, true);
+ sysbus_init_mmio(dev, &s->rom);
+
+ fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
+ if (fcode_filename) {
+ ret = load_image_targphys(fcode_filename, s->prom_addr,
+ FCODE_MAX_ROM_SIZE);
+ }
+
+ if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
+ fprintf(stderr, "tcx: could not load prom '%s'\n", TCX_ROM_FILE);
+ return -1;
+ }
+
/* 8-bit plane */
s->vram = vram_base;
size = s->vram_size;
@@ -598,6 +622,7 @@ static Property tcx_properties[] = {
DEFINE_PROP_UINT16("width", TCXState, width, -1),
DEFINE_PROP_UINT16("height", TCXState, height, -1),
DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
+ DEFINE_PROP_HEX64("prom_addr", TCXState, prom_addr, -1),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index a0d366c..94f7950 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -537,24 +537,27 @@ static void tcx_init(hwaddr addr, int vram_size, int width,
qdev_prop_set_uint16(dev, "width", width);
qdev_prop_set_uint16(dev, "height", height);
qdev_prop_set_uint16(dev, "depth", depth);
+ qdev_prop_set_uint64(dev, "prom_addr", addr);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
+ /* FCode ROM */
+ sysbus_mmio_map(s, 0, addr);
/* 8-bit plane */
- sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
+ sysbus_mmio_map(s, 1, addr + 0x00800000ULL);
/* DAC */
- sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
+ sysbus_mmio_map(s, 2, addr + 0x00200000ULL);
/* TEC (dummy) */
- sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
+ sysbus_mmio_map(s, 3, addr + 0x00700000ULL);
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
- sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
+ sysbus_mmio_map(s, 4, addr + 0x00301000ULL);
if (depth == 24) {
/* 24-bit plane */
- sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
+ sysbus_mmio_map(s, 5, addr + 0x02000000ULL);
/* Control plane */
- sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
+ sysbus_mmio_map(s, 6, addr + 0x0a000000ULL);
} else {
/* THC 8 bit (dummy) */
- sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
+ sysbus_mmio_map(s, 5, addr + 0x00300000ULL);
}
}
diff --git a/pc-bios/QEMU,tcx.bin b/pc-bios/QEMU,tcx.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a8ddd70ef35355c30d7cffd2e1b57f877572a3ca
GIT binary patch
literal 1242
zcmZ8hxl-Fu6xFkZeQXTK&j!qn**AgB64rt)Bt;q~lNw`zm4NNY!htH3naNM2fFJOT
zMvP0-C0(jantVh4Aoo6xa1s^oY*+VceZQe4G)@2MLG!<*wdh7l>uTIJS~6X!TIGUW
zshM@VXjRM)cF`?Cvpk3g+5cZyvh4GctJ2Vej2Eq{TQUo_TT@n;tP8trnS~qIYFqk)
zhb|xDvgIM-Bg7c>5oUxB{jz0fba;q04NWkK6PaYvO+-5+l3=3g9(st(aMT+_eL-Xp
zS>Pzi&MgtCBH<xLBxjJ5X2Lc79I-RN1fw1XiBvht1kn(YTXu$tP?d*~rV&z?I!ewV
zJ7Zj|(TMS;p{r;jh$e$5+cY97nj+_x&zf!;aplYe#j`>2T+^VJL^bn4@j?(SHjQ2t
zEd|kX5Un&ln11eFgno#yNaaORNP4`hK87&@6QdZ1DI_M4RXBxdg)^8_IFChzOIT5u
z!H~jk^eF7dpu!m93VUHFOd`c7!;W<>44SysnK-5@CNQb6GjUewc`PVg!m`57#Dvmm
z3@GeO>{B`k$=I2g^K&Acmyyeps%e))F}jGnFQY6gS1##059<%KZ1A#4ALEvvdw%>e
zkM;3d>ucn+a#3-zc;??@>%~icn>x1s1!}qNqZ=E@Jz|~I4&9}}KNB09WbFFb#!gG(
z`1PwdEAHuaNXTf>u2nBiZp5&MJs<0L2Wf2?yV!gb1@TtAqctg`C&i*;)oQ{(7a~XE
zGJ7O0vf^`tn(q6E@`Zp-oWd%49<d>H*SWGpTE=LIxx+u6Fj88kfi)y3SM>-x)J=C9
ztj2gsy-=+<rzK&q^M#$#-%f;_u6pgJeA=$~#JbecVb$a8uO1oI<H-sC`hLhx)xJJ+
ztoQ9M2i&FJ*5DD5_TItw%8}Y;NPt9)Hx0FCw9lo2d;W-}ZkJu>$&+!Cmg8JiU3z3m
K?1|A9_O(BcTLJ$7
literal 0
HcmV?d00001
diff --git a/pc-bios/README b/pc-bios/README
index b4138d1..7a3e4e9 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -11,8 +11,8 @@
firmware implementation. The goal is to implement a 100% IEEE
1275-1994 (referred to as Open Firmware) compliant firmware.
The included images for PowerPC (for 32 and 64 bit PPC CPUs),
- Sparc32 and Sparc64 are built from OpenBIOS SVN revision
- 1229.
+ Sparc32 (including QEMU,tcx.bin) and Sparc64 are built from OpenBIOS SVN
+ revision 1229.
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
--
1.7.10.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH for-1.7 2/3] sun4m: Add Sun CG3 framebuffer and corresponding OpenBIOS FCode ROM
2013-11-02 16:03 [Qemu-devel] [PATCH for-1.7 0/3] sun4m: Add TCX FCode ROM and support for CG3 framebuffer Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer Mark Cave-Ayland
@ 2013-11-02 16:03 ` Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 3/3] sun4m: Add Sun CG3 framebuffer initialisation function Mark Cave-Ayland
2 siblings, 0 replies; 7+ messages in thread
From: Mark Cave-Ayland @ 2013-11-02 16:03 UTC (permalink / raw)
To: qemu-devel
Cc: Blue Swirl, Bob Breuer, Mark Cave-Ayland, Artyom Tarasenko,
aliguori
The CG3 framebuffer is a simple 8-bit framebuffer for use with operating
systems such as early Solaris that do not have drivers for TCX.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Blue Swirl <blauwirbel@gmail.com>
CC: Bob Breuer <breuerr@mc.net>
CC: Artyom Tarasenko <atar4qemu@gmail.com>
---
Makefile | 2 +-
default-configs/sparc-softmmu.mak | 1 +
hw/display/Makefile.objs | 1 +
hw/display/cg3.c | 359 +++++++++++++++++++++++++++++++++++++
pc-bios/QEMU,cgthree.bin | Bin 0 -> 682 bytes
pc-bios/README | 4 +-
6 files changed, 364 insertions(+), 3 deletions(-)
create mode 100644 hw/display/cg3.c
create mode 100644 pc-bios/QEMU,cgthree.bin
diff --git a/Makefile b/Makefile
index 3235039..8692e6e 100644
--- a/Makefile
+++ b/Makefile
@@ -286,7 +286,7 @@ ifdef INSTALL_BLOBS
BLOBS=bios.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin \
acpi-dsdt.aml q35-acpi-dsdt.aml \
-ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin \
+ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \
pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \
efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
diff --git a/default-configs/sparc-softmmu.mak b/default-configs/sparc-softmmu.mak
index 8fc93dd..ab796b3 100644
--- a/default-configs/sparc-softmmu.mak
+++ b/default-configs/sparc-softmmu.mak
@@ -10,6 +10,7 @@ CONFIG_EMPTY_SLOT=y
CONFIG_PCNET_COMMON=y
CONFIG_LANCE=y
CONFIG_TCX=y
+CONFIG_CG3=y
CONFIG_SLAVIO=y
CONFIG_CS4231=y
CONFIG_GRLIB=y
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index 540df82..7ed76a9 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -28,6 +28,7 @@ obj-$(CONFIG_OMAP) += omap_lcdc.o
obj-$(CONFIG_PXA2XX) += pxa2xx_lcd.o
obj-$(CONFIG_SM501) += sm501.o
obj-$(CONFIG_TCX) += tcx.o
+obj-$(CONFIG_CG3) += cg3.o
obj-$(CONFIG_VGA) += vga.o
diff --git a/hw/display/cg3.c b/hw/display/cg3.c
new file mode 100644
index 0000000..b09bf23
--- /dev/null
+++ b/hw/display/cg3.c
@@ -0,0 +1,359 @@
+/*
+ * QEMU CG3 Frame buffer
+ *
+ * Copyright (c) 2012 Bob Breuer
+ * Copyright (c) 2013 Mark Cave-Ayland
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu-common.h"
+#include "ui/console.h"
+#include "hw/sysbus.h"
+#include "hw/loader.h"
+
+/* #define DEBUG_CG3 */
+
+#define CG3_ROM_FILE "QEMU,cgthree.bin"
+#define FCODE_MAX_ROM_SIZE 0x10000
+
+#define CG3_REG_SIZE 0x20
+#define CG3_VRAM_SIZE 0x100000
+#define CG3_VRAM_OFFSET 0x800000
+
+#ifdef DEBUG_CG3
+#define DPRINTF(fmt, ...) \
+ printf("CG3: " fmt , ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+#define TYPE_CG3 "SUNW,cgthree"
+#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
+
+typedef struct CG3State {
+ SysBusDevice parent_obj;
+
+ QemuConsole *con;
+ qemu_irq irq;
+ hwaddr prom_addr;
+ MemoryRegion vram_mem;
+ MemoryRegion rom;
+ MemoryRegion reg;
+ uint32_t vram_size;
+ int full_update;
+ uint8_t regs[16];
+ uint8_t r[256], g[256], b[256];
+ uint16_t width, height, depth;
+ uint8_t dac_index, dac_state;
+} CG3State;
+
+static void cg3_update_display(void *opaque)
+{
+ CG3State *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
+ const uint8_t *pix;
+ uint32_t *data;
+ uint32_t dval;
+ int x, y, y_start;
+ unsigned int width, height;
+ ram_addr_t page, page_min, page_max;
+
+ if (surface_bits_per_pixel(surface) != 32) {
+ return;
+ }
+ width = s->width;
+ height = s->height;
+
+ y_start = -1;
+ page_min = -1;
+ page_max = 0;
+ page = 0;
+ pix = memory_region_get_ram_ptr(&s->vram_mem);
+ data = (uint32_t *)surface_data(surface);
+
+ for (y = 0; y < height; y++) {
+ int update = s->full_update;
+
+ page = (y * width) & TARGET_PAGE_MASK;
+ update |= memory_region_get_dirty(&s->vram_mem, page, page + width,
+ DIRTY_MEMORY_VGA);
+ if (update) {
+ if (y_start < 0) {
+ y_start = y;
+ }
+ if (page < page_min) {
+ page_min = page;
+ }
+ if (page > page_max) {
+ page_max = page;
+ }
+
+ for (x = 0; x < width; x++) {
+ dval = *pix++;
+ dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];
+ *data++ = dval;
+ }
+ } else {
+ if (y_start >= 0) {
+ dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
+ y_start = -1;
+ }
+ pix += width;
+ data += width;
+ }
+ }
+ s->full_update = 0;
+ if (y_start >= 0) {
+ dpy_gfx_update(s->con, 0, y_start, s->width, y - y_start);
+ }
+ if (page_max >= page_min) {
+ memory_region_reset_dirty(&s->vram_mem,
+ page_min, page_max - page_min + TARGET_PAGE_SIZE,
+ DIRTY_MEMORY_VGA);
+ }
+ /* vsync interrupt? */
+ if (s->regs[0] & 0x80) {
+ s->regs[1] |= 0x80;
+ qemu_irq_raise(s->irq);
+ }
+}
+
+static void cg3_invalidate_display(void *opaque)
+{
+ CG3State *s = opaque;
+
+ memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
+}
+
+static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
+{
+ CG3State *s = opaque;
+ int val;
+
+ switch (addr) {
+ case 0x10:
+ val = s->regs[0];
+ break;
+ case 0x11:
+ val = s->regs[1] | 0x71; /* monitor ID 7, board type = 1 (color) */
+ break;
+ case 0x12 ... 0x1f:
+ val = s->regs[addr - 0x10];
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ DPRINTF("read %02x from reg %x\n", val, (int)addr);
+ return val;
+}
+
+static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ CG3State *s = opaque;
+ uint8_t regval;
+ int i;
+
+ DPRINTF("write %02lx to reg %x size %d\n", val, (int)addr, size);
+
+ switch (addr) {
+ case 0:
+ s->dac_index = val;
+ s->dac_state = 0;
+ break;
+ case 4:
+ /* This register can be written to as either a long word or a byte.
+ * According to the SBus specification, byte transfers are placed
+ * in bits 31-28 */
+ if (size == 1) {
+ val <<= 24;
+ }
+
+ for (i = 0; i < size; i++) {
+ regval = val >> 24;
+
+ switch (s->dac_state) {
+ case 0:
+ s->r[s->dac_index] = regval;
+ s->dac_state++;
+ break;
+ case 1:
+ s->g[s->dac_index] = regval;
+ s->dac_state++;
+ break;
+ case 2:
+ s->b[s->dac_index] = regval;
+ /* Index autoincrement */
+ s->dac_index = (s->dac_index + 1) & 255;
+ default:
+ s->dac_state = 0;
+ break;
+ }
+ val <<= 8;
+ }
+ s->full_update = 1;
+ break;
+ case 0x10:
+ s->regs[0] = val;
+ break;
+ case 0x11:
+ if (s->regs[1] & 0x80) {
+ /* clear interrupt */
+ s->regs[1] &= ~0x80;
+ qemu_irq_lower(s->irq);
+ }
+ break;
+ case 0x12 ... 0x1f:
+ s->regs[addr - 0x10] = val;
+ break;
+ default:
+ break;
+ }
+}
+
+static const MemoryRegionOps cg3_reg_ops = {
+ .read = cg3_reg_read,
+ .write = cg3_reg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static const GraphicHwOps cg3_ops = {
+ .invalidate = cg3_invalidate_display,
+ .gfx_update = cg3_update_display,
+};
+
+static int cg3_init1(SysBusDevice *dev)
+{
+ CG3State *s = CG3(dev);
+ int ret;
+ char *fcode_filename;
+
+ /* FCode ROM */
+ memory_region_init_ram(&s->rom, NULL, "cg3.prom", FCODE_MAX_ROM_SIZE);
+ vmstate_register_ram_global(&s->rom);
+ memory_region_set_readonly(&s->rom, true);
+ sysbus_init_mmio(dev, &s->rom);
+
+ fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
+ if (fcode_filename) {
+ ret = load_image_targphys(fcode_filename, s->prom_addr,
+ FCODE_MAX_ROM_SIZE);
+ }
+
+ if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
+ fprintf(stderr, "cg3: could not load prom '%s'\n", CG3_ROM_FILE);
+ exit(1);
+ }
+
+ memory_region_init_io(&s->reg, NULL, &cg3_reg_ops, s, "cg3.reg",
+ CG3_REG_SIZE);
+ sysbus_init_mmio(dev, &s->reg);
+
+ memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size);
+ vmstate_register_ram_global(&s->vram_mem);
+ sysbus_init_mmio(dev, &s->vram_mem);
+
+ sysbus_init_irq(dev, &s->irq);
+
+ s->con = graphic_console_init(DEVICE(dev), &cg3_ops, s);
+ qemu_console_resize(s->con, s->width, s->height);
+
+ return 0;
+}
+
+static int vmstate_cg3_post_load(void *opaque, int version_id)
+{
+ CG3State *s = opaque;
+
+ cg3_invalidate_display(s);
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_cg3 = {
+ .name = "cg3",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = vmstate_cg3_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16(height, CG3State),
+ VMSTATE_UINT16(width, CG3State),
+ VMSTATE_UINT16(depth, CG3State),
+ VMSTATE_BUFFER(r, CG3State),
+ VMSTATE_BUFFER(g, CG3State),
+ VMSTATE_BUFFER(b, CG3State),
+ VMSTATE_UINT8(dac_index, CG3State),
+ VMSTATE_UINT8(dac_state, CG3State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void cg3_reset(DeviceState *d)
+{
+ CG3State *s = CG3(d);
+
+ /* Initialize palette */
+ memset(s->r, 0, 256);
+ memset(s->g, 0, 256);
+ memset(s->b, 0, 256);
+
+ s->dac_state = 0;
+ s->full_update = 1;
+ qemu_irq_lower(s->irq);
+}
+
+static Property cg3_properties[] = {
+ DEFINE_PROP_HEX32("vram_size", CG3State, vram_size, -1),
+ DEFINE_PROP_UINT16("width", CG3State, width, -1),
+ DEFINE_PROP_UINT16("height", CG3State, height, -1),
+ DEFINE_PROP_UINT16("depth", CG3State, depth, -1),
+ DEFINE_PROP_HEX64("prom_addr", CG3State, prom_addr, -1),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void cg3_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = cg3_init1;
+ dc->reset = cg3_reset;
+ dc->vmsd = &vmstate_cg3;
+ dc->props = cg3_properties;
+}
+
+static const TypeInfo cg3_info = {
+ .name = TYPE_CG3,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(CG3State),
+ .class_init = cg3_class_init,
+};
+
+static void cg3_register_types(void)
+{
+ type_register_static(&cg3_info);
+}
+
+type_init(cg3_register_types)
diff --git a/pc-bios/QEMU,cgthree.bin b/pc-bios/QEMU,cgthree.bin
new file mode 100644
index 0000000000000000000000000000000000000000..e2ecfc6f34edace2d39b411454768cd3a1366e71
GIT binary patch
literal 682
zcmZ8e&2G~`5Z+0gc-$n^UOTi&0g*FU#DYkz#DQbW0S*=7?8MvHkl2xbK)LnKYb2K*
zBUu~u=-%K3cn#iwS?2_onfbn%Z)SGq58l0EtZ`Q&lfN9MzqVOxx7k(PNme4BMoH#=
zivp3j-=iQ8k%<yv&-?!+LlMoxyv{cE{3sBsJanf~p4C*7s6`YDce>8Sfzs-#X)$;6
z^-3Tsv9&L;EfJPgiMqsw@+h&XydhCj{zzi$X=So^j0Bx~lQH(Z#4ZK5is@0%Rl%eC
z5|8D03yt5<1lt1(ILS?^6wCxNc+8urn1e~YCCAY8czfxu+$e4sL~+S=1(PBtyeZM%
zlW}OrzC`<3QT=Ssl0}k^@Uh%t|LVQ!tYQCOM~zM-cCd@q1KNa6CHCqa72yyuka&Wp
z71w9;JWPdX0M~;kTP^%G40-SR(}&M5Cu7g`-gpxjlsKg6o3{>ofdh0NU<zO0D_M){
zeh{Q0%fQ4o>X)z_UBY4nKXx?aOrnW86}1m{QZ<BH^+^dB1Ppbc`aWQ)M_holRo}+7
zD9%%*AXdAj(H)i6ZD#CL(Atr>w@l(FPf|A%aVEgznpzwj-d*}}apTYOA{Eqx8&}sK
p&(9|pu1Cq<Ec8>#38l*qW4qL?Gb_?8NwYAzA=bhnJgM-E{ROoYtgZk6
literal 0
HcmV?d00001
diff --git a/pc-bios/README b/pc-bios/README
index 7a3e4e9..ca3b8c1 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -11,8 +11,8 @@
firmware implementation. The goal is to implement a 100% IEEE
1275-1994 (referred to as Open Firmware) compliant firmware.
The included images for PowerPC (for 32 and 64 bit PPC CPUs),
- Sparc32 (including QEMU,tcx.bin) and Sparc64 are built from OpenBIOS SVN
- revision 1229.
+ Sparc32 (including QEMU,tcx.bin and QEMU,cgthree.bin) and Sparc64 are built
+ from OpenBIOS SVN revision 1229.
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
--
1.7.10.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH for-1.7 3/3] sun4m: Add Sun CG3 framebuffer initialisation function
2013-11-02 16:03 [Qemu-devel] [PATCH for-1.7 0/3] sun4m: Add TCX FCode ROM and support for CG3 framebuffer Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 2/3] sun4m: Add Sun CG3 framebuffer and corresponding OpenBIOS FCode ROM Mark Cave-Ayland
@ 2013-11-02 16:03 ` Mark Cave-Ayland
2 siblings, 0 replies; 7+ messages in thread
From: Mark Cave-Ayland @ 2013-11-02 16:03 UTC (permalink / raw)
To: qemu-devel
Cc: Blue Swirl, Bob Breuer, Mark Cave-Ayland, Artyom Tarasenko,
aliguori
In order to allow the user to choose the framebuffer for sparc-softmmu, add
-vga tcx and -vga cg3 options to the QEMU command line. If no option is
specified, the default TCX framebuffer is used.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Blue Swirl <blauwirbel@gmail.com>
CC: Bob Breuer <breuerr@mc.net>
CC: Artyom Tarasenko <atar4qemu@gmail.com>
---
hw/sparc/sun4m.c | 60 +++++++++++++++++++++++++++++++++++++++++++++--
include/sysemu/sysemu.h | 1 +
vl.c | 24 +++++++++++++++++++
3 files changed, 83 insertions(+), 2 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 94f7950..4c6c450 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -561,6 +561,31 @@ static void tcx_init(hwaddr addr, int vram_size, int width,
}
}
+static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
+ int height, int depth)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+
+ dev = qdev_create(NULL, "SUNW,cgthree");
+ qdev_prop_set_uint32(dev, "vram_size", vram_size);
+ qdev_prop_set_uint16(dev, "width", width);
+ qdev_prop_set_uint16(dev, "height", height);
+ qdev_prop_set_uint16(dev, "depth", depth);
+ qdev_prop_set_uint64(dev, "prom_addr", addr);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+
+ /* FCode ROM */
+ sysbus_mmio_map(s, 0, addr);
+ /* DAC */
+ sysbus_mmio_map(s, 1, addr + 0x400000ULL);
+ /* 8-bit plane */
+ sysbus_mmio_map(s, 2, addr + 0x800000ULL);
+
+ sysbus_connect_irq(s, 0, irq);
+}
+
/* NCR89C100/MACIO Internal ID register */
#define TYPE_MACIO_ID_REGISTER "macio_idreg"
@@ -918,8 +943,39 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
}
num_vsimms = 0;
if (num_vsimms == 0) {
- tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
- graphic_depth);
+ if (vga_interface_type == VGA_CG3) {
+ if (graphic_depth != 8) {
+ fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
+ exit(1);
+ }
+
+ if (!(graphic_width == 1024 && graphic_height == 768) &&
+ !(graphic_width == 1152 && graphic_height == 900)) {
+ fprintf(stderr, "qemu: Unsupported resolution: %d x %d\n",
+ graphic_width, graphic_height);
+ exit(1);
+ }
+
+ /* sbus irq 5 */
+ cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
+ graphic_width, graphic_height, graphic_depth);
+ } else {
+ /* If no display specified, default to TCX */
+ if (graphic_depth != 8 && graphic_depth != 24) {
+ fprintf(stderr, "qemu: Unsupported depth: %d\n",
+ graphic_depth);
+ exit(1);
+ }
+
+ if (!(graphic_width == 1024 && graphic_height == 768)) {
+ fprintf(stderr, "qemu: Unsupported resolution: %d x %d\n",
+ graphic_width, graphic_height);
+ exit(1);
+ }
+
+ tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
+ graphic_depth);
+ }
}
for (i = num_vsimms; i < MAX_VSIMMS; i++) {
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index cd5791e..2698f6d 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -104,6 +104,7 @@ extern int autostart;
typedef enum {
VGA_NONE, VGA_STD, VGA_CIRRUS, VGA_VMWARE, VGA_XENFB, VGA_QXL,
+ VGA_TCX, VGA_CG3,
} VGAInterfaceType;
extern int vga_interface_type;
diff --git a/vl.c b/vl.c
index efbff65..e11f4cf 100644
--- a/vl.c
+++ b/vl.c
@@ -2082,6 +2082,16 @@ static bool qxl_vga_available(void)
return object_class_by_name("qxl-vga");
}
+static bool tcx_vga_available(void)
+{
+ return object_class_by_name("SUNW,tcx");
+}
+
+static bool cg3_vga_available(void)
+{
+ return object_class_by_name("SUNW,cgthree");
+}
+
static void select_vgahw (const char *p)
{
const char *opts;
@@ -2117,6 +2127,20 @@ static void select_vgahw (const char *p)
fprintf(stderr, "Error: QXL VGA not available\n");
exit(0);
}
+ } else if (strstart(p, "tcx", &opts)) {
+ if (tcx_vga_available()) {
+ vga_interface_type = VGA_TCX;
+ } else {
+ fprintf(stderr, "Error: TCX framebuffer not available\n");
+ exit(0);
+ }
+ } else if (strstart(p, "cg3", &opts)) {
+ if (cg3_vga_available()) {
+ vga_interface_type = VGA_CG3;
+ } else {
+ fprintf(stderr, "Error: CG3 framebuffer not available\n");
+ exit(0);
+ }
} else if (!strstart(p, "none", &opts)) {
invalid_vga:
fprintf(stderr, "Unknown vga type: %s\n", p);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer
@ 2013-12-19 12:59 Artyom Tarasenko
2013-12-19 19:27 ` Mark Cave-Ayland
0 siblings, 1 reply; 7+ messages in thread
From: Artyom Tarasenko @ 2013-12-19 12:59 UTC (permalink / raw)
To: Mark Cave-Ayland; +Cc: Blue Swirl, peter, Bob Breuer, qemu-devel, aliguori
Hi Mark,
this patch breaks booting with OBP:
Probing /iommu@0,10000000/sbus@0,10001000 at 5,0 espdma esp sd st
SUNW,bpp ledma le
Probing /iommu@0,10000000/sbus@0,10001000 at 4,0 SUNW,CS4231 power-management
Probing /iommu@0,10000000/sbus@0,10001000 at 1,0 Nothing there
Probing /iommu@0,10000000/sbus@0,10001000 at 2,0 Nothing there
Probing /iommu@0,10000000/sbus@0,10001000 at 3,0 SUNW,tcx Memory
Address not Aligned
^^^^ After the unaligned access OBP is not properly initialized.
See the bug 1262081, reported by Peter Bartoli.
Artyom
On Sat, Nov 2, 2013 at 5:03 PM, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
> Upstream OpenBIOS now implements SBus probing in order to determine the
> contents of a physical bus slot, which is required to allow OpenBIOS to
> identify the framebuffer without help from the fw_cfg interface.
>
> SBus probing works by detecting the presence of an FCode program
> (effectively tokenised Forth) at the base address of each slot, and if
> present executes it so that it creates its own device node in the
> OpenBIOS device tree.
>
> The FCode ROM is generated as part of the OpenBIOS build and should
> generally be updated at the same time.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> CC: Blue Swirl <blauwirbel@gmail.com>
> CC: Bob Breuer <breuerr@mc.net>
> CC: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
> Makefile | 2 +-
> hw/display/tcx.c | 27 ++++++++++++++++++++++++++-
> hw/sparc/sun4m.c | 17 ++++++++++-------
> pc-bios/QEMU,tcx.bin | Bin 0 -> 1242 bytes
> pc-bios/README | 4 ++--
> 5 files changed, 39 insertions(+), 11 deletions(-)
> create mode 100644 pc-bios/QEMU,tcx.bin
>
> diff --git a/Makefile b/Makefile
> index b15003f..3235039 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -286,7 +286,7 @@ ifdef INSTALL_BLOBS
> BLOBS=bios.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
> vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin \
> acpi-dsdt.aml q35-acpi-dsdt.aml \
> -ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc \
> +ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin \
> pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \
> pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \
> efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
> diff --git a/hw/display/tcx.c b/hw/display/tcx.c
> index 24876d3..06bf66f 100644
> --- a/hw/display/tcx.c
> +++ b/hw/display/tcx.c
> @@ -25,8 +25,12 @@
> #include "qemu-common.h"
> #include "ui/console.h"
> #include "ui/pixel_ops.h"
> +#include "hw/loader.h"
> #include "hw/sysbus.h"
>
> +#define TCX_ROM_FILE "QEMU,tcx.bin"
> +#define FCODE_MAX_ROM_SIZE 0x10000
> +
> #define MAXX 1024
> #define MAXY 768
> #define TCX_DAC_NREGS 16
> @@ -43,6 +47,8 @@ typedef struct TCXState {
> QemuConsole *con;
> uint8_t *vram;
> uint32_t *vram24, *cplane;
> + hwaddr prom_addr;
> + MemoryRegion rom;
> MemoryRegion vram_mem;
> MemoryRegion vram_8bit;
> MemoryRegion vram_24bit;
> @@ -529,14 +535,32 @@ static int tcx_init1(SysBusDevice *dev)
> {
> TCXState *s = TCX(dev);
> ram_addr_t vram_offset = 0;
> - int size;
> + int size, ret;
> uint8_t *vram_base;
> + char *fcode_filename;
>
> memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram",
> s->vram_size * (1 + 4 + 4));
> vmstate_register_ram_global(&s->vram_mem);
> vram_base = memory_region_get_ram_ptr(&s->vram_mem);
>
> + /* FCode ROM */
> + memory_region_init_ram(&s->rom, NULL, "tcx.prom", FCODE_MAX_ROM_SIZE);
> + vmstate_register_ram_global(&s->rom);
> + memory_region_set_readonly(&s->rom, true);
> + sysbus_init_mmio(dev, &s->rom);
> +
> + fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
> + if (fcode_filename) {
> + ret = load_image_targphys(fcode_filename, s->prom_addr,
> + FCODE_MAX_ROM_SIZE);
> + }
> +
> + if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
> + fprintf(stderr, "tcx: could not load prom '%s'\n", TCX_ROM_FILE);
> + return -1;
> + }
> +
> /* 8-bit plane */
> s->vram = vram_base;
> size = s->vram_size;
> @@ -598,6 +622,7 @@ static Property tcx_properties[] = {
> DEFINE_PROP_UINT16("width", TCXState, width, -1),
> DEFINE_PROP_UINT16("height", TCXState, height, -1),
> DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
> + DEFINE_PROP_HEX64("prom_addr", TCXState, prom_addr, -1),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
> index a0d366c..94f7950 100644
> --- a/hw/sparc/sun4m.c
> +++ b/hw/sparc/sun4m.c
> @@ -537,24 +537,27 @@ static void tcx_init(hwaddr addr, int vram_size, int width,
> qdev_prop_set_uint16(dev, "width", width);
> qdev_prop_set_uint16(dev, "height", height);
> qdev_prop_set_uint16(dev, "depth", depth);
> + qdev_prop_set_uint64(dev, "prom_addr", addr);
> qdev_init_nofail(dev);
> s = SYS_BUS_DEVICE(dev);
> + /* FCode ROM */
> + sysbus_mmio_map(s, 0, addr);
> /* 8-bit plane */
> - sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
> + sysbus_mmio_map(s, 1, addr + 0x00800000ULL);
> /* DAC */
> - sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
> + sysbus_mmio_map(s, 2, addr + 0x00200000ULL);
> /* TEC (dummy) */
> - sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
> + sysbus_mmio_map(s, 3, addr + 0x00700000ULL);
> /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
> - sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
> + sysbus_mmio_map(s, 4, addr + 0x00301000ULL);
> if (depth == 24) {
> /* 24-bit plane */
> - sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
> + sysbus_mmio_map(s, 5, addr + 0x02000000ULL);
> /* Control plane */
> - sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
> + sysbus_mmio_map(s, 6, addr + 0x0a000000ULL);
> } else {
> /* THC 8 bit (dummy) */
> - sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
> + sysbus_mmio_map(s, 5, addr + 0x00300000ULL);
> }
> }
>
> diff --git a/pc-bios/QEMU,tcx.bin b/pc-bios/QEMU,tcx.bin
<cut>
--
Regards,
Artyom Tarasenko
linux/sparc and solaris/sparc under qemu blog:
http://tyom.blogspot.com/search/label/qemu
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer
2013-12-19 12:59 [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer Artyom Tarasenko
@ 2013-12-19 19:27 ` Mark Cave-Ayland
2013-12-23 3:04 ` Peter Bartoli
0 siblings, 1 reply; 7+ messages in thread
From: Mark Cave-Ayland @ 2013-12-19 19:27 UTC (permalink / raw)
To: Artyom Tarasenko; +Cc: Blue Swirl, peter, Bob Breuer, qemu-devel, aliguori
On 19/12/13 12:59, Artyom Tarasenko wrote:
> Hi Mark,
>
> this patch breaks booting with OBP:
>
> Probing /iommu@0,10000000/sbus@0,10001000 at 5,0 espdma esp sd st
> SUNW,bpp ledma le
> Probing /iommu@0,10000000/sbus@0,10001000 at 4,0 SUNW,CS4231 power-management
> Probing /iommu@0,10000000/sbus@0,10001000 at 1,0 Nothing there
> Probing /iommu@0,10000000/sbus@0,10001000 at 2,0 Nothing there
> Probing /iommu@0,10000000/sbus@0,10001000 at 3,0 SUNW,tcx Memory
> Address not Aligned
>
> ^^^^ After the unaligned access OBP is not properly initialized.
> See the bug 1262081, reported by Peter Bartoli.
>
> Artyom
Ah... I wonder if OBP doesn't like something in the QEMU,tcx.bin FCode
initialisation function? If you temporarily rename the file (which can
be found in the share directory) to something else, does boot start to
work again?
Thinking about it, I suspect I'll need to add some code to the OpenBIOS
FCode ROMs so that they only initialise if OpenBIOS is detected. This is
because there is code there that tries to get information from QEMU
about the screen width/height/depth etc. which will obviously fail on OBP.
ATB,
Mark.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer
2013-12-19 19:27 ` Mark Cave-Ayland
@ 2013-12-23 3:04 ` Peter Bartoli
0 siblings, 0 replies; 7+ messages in thread
From: Peter Bartoli @ 2013-12-23 3:04 UTC (permalink / raw)
To: Mark Cave-Ayland
Cc: Blue Swirl, Bob Breuer, qemu-devel, Artyom Tarasenko, aliguori
[-- Attachment #1: Type: text/plain, Size: 1481 bytes --]
-peter
On Dec 19, 2013, at 11:27 AM, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> wrote:
> On 19/12/13 12:59, Artyom Tarasenko wrote:
>
>> Hi Mark,
>>
>> this patch breaks booting with OBP:
>>
>> Probing /iommu@0,10000000/sbus@0,10001000 at 5,0 espdma esp sd st
>> SUNW,bpp ledma le
>> Probing /iommu@0,10000000/sbus@0,10001000 at 4,0 SUNW,CS4231 power-management
>> Probing /iommu@0,10000000/sbus@0,10001000 at 1,0 Nothing there
>> Probing /iommu@0,10000000/sbus@0,10001000 at 2,0 Nothing there
>> Probing /iommu@0,10000000/sbus@0,10001000 at 3,0 SUNW,tcx Memory
>> Address not Aligned
>>
>> ^^^^ After the unaligned access OBP is not properly initialized.
>> See the bug 1262081, reported by Peter Bartoli.
>>
>> Artyom
>
> Ah... I wonder if OBP doesn't like something in the QEMU,tcx.bin FCode initialisation function? If you temporarily rename the file (which can be found in the share directory) to something else, does boot start to work again?
>
> Thinking about it, I suspect I'll need to add some code to the OpenBIOS FCode ROMs so that they only initialise if OpenBIOS is detected. This is because there is code there that tries to get information from QEMU about the screen width/height/depth etc. which will obviously fail on OBP.
>
>
> ATB,
>
> Mark.
Out of curiosity, and please pardon my ignorance and separate bug filing about the tcx not working with OBP ... but why is it that this doesn't work?
-peter
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-12-23 3:04 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-11-02 16:03 [Qemu-devel] [PATCH for-1.7 0/3] sun4m: Add TCX FCode ROM and support for CG3 framebuffer Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 2/3] sun4m: Add Sun CG3 framebuffer and corresponding OpenBIOS FCode ROM Mark Cave-Ayland
2013-11-02 16:03 ` [Qemu-devel] [PATCH for-1.7 3/3] sun4m: Add Sun CG3 framebuffer initialisation function Mark Cave-Ayland
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2013-12-19 12:59 [Qemu-devel] [PATCH for-1.7 1/3] sun4m: Add FCode ROM for TCX framebuffer Artyom Tarasenko
2013-12-19 19:27 ` Mark Cave-Ayland
2013-12-23 3:04 ` Peter Bartoli
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