[Qemu-devel] [PATCH 00/14] VSX Stage 4

[Tom Musta <tommusta@gmail.com>]

This is the fourth and final series of patches that add emulation support
to QEMU for the PowerPC Vector Scalar Extension (VSX).

This series adds the instructions that were newly introduced with Power ISA
V2.07.  This includes 3 scalar load instructions, 2 scalar store instructions,
7 standard single precision scalar arithmetic instructions, 8 scalar single
precision fused multiply/add instructions, two integer-to-single-precision
conversion instructions and 3 vector logical instructions.

The single-precision scalar arithmetic instructions all interpret the most
significant 64 bits of a VSR as a single precision floating point number
stored in double precision format (similar to the standard PowerPC floating
point single precision instructions).  Thus a common theme in the supporting
code is rounding of an intermediate double-precision number to single 
precision.

Tom Musta (14):
  VSX Stage 4: Add VSX 2.07 Flag
  VSX Stage 4: Refactor lxsdx
  VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx
  VSX Stage 4: Refactor stxsdx
  VSX Stage 4: Add stxsiwx and stxsspx
  VSX Stage 4: Add xsaddsp and xssubsp
  VSX Stage 4: Add xsmulsp
  VSX Stage 4: Add xsdivsp
  VSX Stage 4: Add xsresp
  VSX Stage 4: Add xssqrtsp
  VSX Stage 4: add xsrsqrtesp
  VSX Stage 4: Add Scalar SP Fused Multiply-Adds
  VSX Stage 4: Add xscvsxdsp and xscvuxdsp
  VSX Stage 4: Add xxleqv, xxlnand and xxlorc

 target-ppc/cpu.h            |    4 +-
 target-ppc/fpu_helper.c     |  191 ++++++++++++++++++++++++++++---------------
 target-ppc/helper.h         |   18 ++++
 target-ppc/translate.c      |  110 +++++++++++++++++++------
 target-ppc/translate_init.c |    2 +-
 5 files changed, 232 insertions(+), 93 deletions(-)