From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3R-0007CG-Tj for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE3M-0006Bp-25 for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:37 -0500 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]:61591) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3L-0006Ar-Js for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:31 -0500 Received: by mail-pa0-f41.google.com with SMTP id rd3so485083pab.28 for ; Wed, 06 Nov 2013 17:06:30 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.06.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:06:30 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:04:33 +1000 Message-Id: <1383786324-18415-11-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 10/61] target-i386: Remove gen_op_lds_T0_A0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Replace its users by gen_op_ld_v with the MO_SIGN bit set. Signed-off-by: Richard Henderson --- target-i386/translate.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 1f0c441..42620e8 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -576,11 +576,6 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg) } #endif -static inline void gen_op_lds_T0_A0(DisasContext *s, int idx) -{ - tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, s->mem_index, idx | MO_LE | MO_SIGN); -} - static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0) { tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE); @@ -5697,7 +5692,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (b & 8) { - gen_op_lds_T0_A0(s, ot); + gen_op_ld_v(s, ot | MO_SIGN, cpu_T[0], cpu_A0); } else { gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } @@ -6009,7 +6004,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 3: default: - gen_op_lds_T0_A0(s, MO_16); + gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); break; @@ -6048,7 +6043,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 3: default: - gen_op_lds_T0_A0(s, MO_16); + gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); break; @@ -7790,7 +7785,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (d_ot == MO_64) { - gen_op_lds_T0_A0(s, MO_32); + gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0); } else { gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); } -- 1.8.3.1