From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37610) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3Z-0007ML-Cr for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE3T-0006D5-A3 for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:45 -0500 Received: from mail-pb0-x22c.google.com ([2607:f8b0:400e:c01::22c]:42571) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3T-0006Cy-2P for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:39 -0500 Received: by mail-pb0-f44.google.com with SMTP id rp8so310583pbb.3 for ; Wed, 06 Nov 2013 17:06:38 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.06.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:06:37 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:04:36 +1000 Message-Id: <1383786324-18415-14-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 13/61] target-i386: Remove gen_op_st_T1_A0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Propagate its definition into all users. Signed-off-by: Richard Henderson --- target-i386/translate.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 6b7c89e..f07fca0 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -586,11 +586,6 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0) tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE); } -static inline void gen_op_st_T1_A0(DisasContext *s, int idx) -{ - gen_op_st_v(s, idx, cpu_T[1], cpu_A0); -} - static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) { if (d == OR_TMP0) { @@ -2487,7 +2482,7 @@ static void gen_push_T1(DisasContext *s) gen_op_movq_A0_reg(R_ESP); if (s->dflag) { gen_op_addq_A0_im(-8); - gen_op_st_T1_A0(s, MO_64); + gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0); } else { gen_op_addq_A0_im(-2); gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); @@ -2509,7 +2504,7 @@ static void gen_push_T1(DisasContext *s) gen_op_andl_A0_ffff(); gen_op_addl_A0_seg(s, R_SS); } - gen_op_st_T1_A0(s, s->dflag + 1); + gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0); if (s->ss32 && !s->addseg) gen_op_mov_reg_A0(1, R_ESP); -- 1.8.3.1