From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37624) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3b-0007PK-Je for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE3V-0006De-MB for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:47 -0500 Received: from mail-pa0-x22e.google.com ([2607:f8b0:400e:c03::22e]:48380) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3V-0006DN-EZ for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:41 -0500 Received: by mail-pa0-f46.google.com with SMTP id rd3so480112pab.19 for ; Wed, 06 Nov 2013 17:06:40 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.06.38 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:06:39 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:04:37 +1000 Message-Id: <1383786324-18415-15-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 14/61] target-i386: Fix typo in gen_push_T1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org By inspection, obviously we should be storing T[1] not T[0]. This could only happen for x86_64 in 64-bit mode with 0x66 prefix to call insn -- i.e. never. Signed-off-by: Richard Henderson --- target-i386/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index f07fca0..e89991e 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2485,7 +2485,7 @@ static void gen_push_T1(DisasContext *s) gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0); } else { gen_op_addq_A0_im(-2); - gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); + gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0); } gen_op_mov_reg_A0(2, R_ESP); } else -- 1.8.3.1