From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37742) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3o-0007gw-8K for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE3i-0006G9-BX for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:00 -0500 Received: from mail-pd0-x235.google.com ([2607:f8b0:400e:c02::235]:48604) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3i-0006G3-4B for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:06:54 -0500 Received: by mail-pd0-f181.google.com with SMTP id x10so308460pdj.12 for ; Wed, 06 Nov 2013 17:06:53 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.06.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:06:52 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:04:42 +1000 Message-Id: <1383786324-18415-20-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 19/61] target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org For the 16 and 32-bit cases, we don't need to truncate via a temporary register. Signed-off-by: Richard Henderson --- target-i386/translate.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index c433cc3..7b40805 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1259,8 +1259,7 @@ static inline void gen_ins(DisasContext *s, int ot) case of page fault. */ gen_op_movl_T0_0(); gen_op_st_v(s, ot, cpu_T[0], cpu_A0); - gen_op_mov_TN_reg(MO_16, 1, R_EDX); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); gen_op_st_v(s, ot, cpu_T[0], cpu_A0); @@ -1277,8 +1276,7 @@ static inline void gen_outs(DisasContext *s, int ot) gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); - gen_op_mov_TN_reg(MO_16, 1, R_EDX); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); @@ -3839,8 +3837,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ot = MO_64; } - gen_op_mov_TN_reg(MO_32, 0, reg); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[reg]); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, cpu_T[0], tcg_const_i32(8 << ot)); -- 1.8.3.1