From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3v-0007rR-NK for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE3p-0006HY-SU for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:07 -0500 Received: from mail-pb0-x229.google.com ([2607:f8b0:400e:c01::229]:62331) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3p-0006HT-LN for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:01 -0500 Received: by mail-pb0-f41.google.com with SMTP id wy17so311653pbc.0 for ; Wed, 06 Nov 2013 17:07:00 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.06.58 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:07:00 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:04:45 +1000 Message-Id: <1383786324-18415-23-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 22/61] target-i386: Tidy extend + move List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org For the known MO_32/MO_64 cases, we don't need to extend a 32-bit temp into a 64-bit temp before storing into the hardware register. We do need the extension for the MO_8/MO_16 cases, in order for the deposit_tl operation to work, so leave those alone. Signed-off-by: Richard Henderson --- target-i386/translate.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 4a9bd14..746eda1 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -3538,16 +3538,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_mov_reg_T0(MO_32, reg); + tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32); break; case 0x150: /* movmskpd */ rm = (modrm & 7) | REX_B(s); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_mov_reg_T0(MO_32, reg); + tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32); break; case 0x02a: /* cvtpi2ps */ case 0x12a: /* cvtpi2pd */ @@ -3731,9 +3729,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0); } - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); reg = ((modrm >> 3) & 7) | rex_r; - gen_op_mov_reg_T0(MO_32, reg); + tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32); break; case 0x138: @@ -4229,8 +4226,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(CPUX86State, xmm_regs[reg].XMM_L(val & 3))); if (mod == 3) { - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_mov_reg_v(ot, rm, cpu_T[0]); + tcg_gen_extu_i32_tl(cpu_regs[rm], cpu_tmp2_i32); } else { tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUL); @@ -4241,7 +4237,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(CPUX86State, xmm_regs[reg].XMM_Q(val & 1))); if (mod == 3) { - gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); + tcg_gen_mov_i64(cpu_regs[rm], cpu_tmp1_i64); } else { tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); -- 1.8.3.1