From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37801) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3y-0007tg-4b for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE3s-0006Hu-9O for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:10 -0500 Received: from mail-pa0-x22e.google.com ([2607:f8b0:400e:c03::22e]:33125) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE3s-0006Ho-2A for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:04 -0500 Received: by mail-pa0-f46.google.com with SMTP id rd3so480515pab.19 for ; Wed, 06 Nov 2013 17:07:03 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.07.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:07:02 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:04:46 +1000 Message-Id: <1383786324-18415-24-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 23/61] target-i386: Remove gen_op_movl_T0_0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Propagate its definition into all users. Signed-off-by: Richard Henderson --- target-i386/translate.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 746eda1..a382c41 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_movl_T0_0(void) -{ - tcg_gen_movi_tl(cpu_T[0], 0); -} - static inline void gen_op_movl_T0_im(int32_t val) { tcg_gen_movi_tl(cpu_T[0], val); @@ -1257,7 +1252,7 @@ static inline void gen_ins(DisasContext *s, int ot) gen_string_movl_A0_EDI(s); /* Note: we must do this dummy write first to be restartable in case of page fault. */ - gen_op_movl_T0_0(); + tcg_gen_movi_tl(cpu_T[0], 0); gen_op_st_v(s, ot, cpu_T[0], cpu_A0); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); @@ -3271,7 +3266,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_lea_modrm(env, s, modrm); gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); - gen_op_movl_T0_0(); + tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); @@ -3286,7 +3281,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_lea_modrm(env, s, modrm); gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg].XMM_Q(0))); - gen_op_movl_T0_0(); + tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); } else { @@ -3507,13 +3502,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (is_xmm) { gen_op_movl_T0_im(val); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); - gen_op_movl_T0_0(); + tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); op1_offset = offsetof(CPUX86State,xmm_t0); } else { gen_op_movl_T0_im(val); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); - gen_op_movl_T0_0(); + tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); op1_offset = offsetof(CPUX86State,mmx_t0); } @@ -4716,7 +4711,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, xor_zero: /* xor reg, reg optimisation */ set_cc_op(s, CC_OP_CLR); - gen_op_movl_T0_0(); + tcg_gen_movi_tl(cpu_T[0], 0); gen_op_mov_reg_T0(ot, reg); break; } else { -- 1.8.3.1