From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37903) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE4E-0008DA-5K for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE47-0006M8-W8 for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:25 -0500 Received: from mail-pb0-x233.google.com ([2607:f8b0:400e:c01::233]:34767) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE47-0006Ly-Pw for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:07:19 -0500 Received: by mail-pb0-f51.google.com with SMTP id xa7so301671pbc.24 for ; Wed, 06 Nov 2013 17:07:18 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.07.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:07:18 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:04:52 +1000 Message-Id: <1383786324-18415-30-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 29/61] target-i386: Remove gen_op_andl_T0_im List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Replace it with its definition. Signed-off-by: Richard Henderson --- target-i386/translate.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index b8a8954..9a5f704 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_andl_T0_im(uint32_t val) -{ - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); -} - static inline void gen_op_movl_T0_T1(void) { tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); @@ -7353,8 +7348,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); gen_add_A0_im(s, 2); tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); - if (!s->dflag) - gen_op_andl_T0_im(0xffffff); + if (s->dflag == 0) { + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); + } gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); break; case 1: @@ -7416,8 +7412,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); gen_add_A0_im(s, 2); tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); - if (!s->dflag) - gen_op_andl_T0_im(0xffffff); + if (s->dflag == 0) { + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); + } gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); } break; @@ -7516,8 +7513,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0); gen_add_A0_im(s, 2); gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); - if (!s->dflag) - gen_op_andl_T0_im(0xffffff); + if (s->dflag == 0) { + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); + } if (op == 2) { tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); -- 1.8.3.1