From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38267) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE55-0000UX-Uc for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE50-0006Xf-1U for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:19 -0500 Received: from mail-pb0-x236.google.com ([2607:f8b0:400e:c01::236]:44013) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE4z-0006Xa-PQ for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:13 -0500 Received: by mail-pb0-f54.google.com with SMTP id ro12so305155pbb.41 for ; Wed, 06 Nov 2013 17:08:12 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.08.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:08:12 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:05:13 +1000 Message-Id: <1383786324-18415-51-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 50/61] target-i386: Rewrite leave List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Unify the code across stack pointer widths. Fix the note about not updating ESP before the potential exception. Signed-off-by: Richard Henderson --- target-i386/translate.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 99b8e9e..c663c6f 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2396,6 +2396,20 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]); } +static void gen_leave(DisasContext *s) +{ + TCGMemOp d_ot = mo_pushpop(s, s->dflag); + TCGMemOp a_ot = mo_stacksize(s); + + gen_lea_v_seg(s, a_ot, cpu_regs[R_EBP], R_SS, -1); + gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0); + + tcg_gen_addi_tl(cpu_T[1], cpu_regs[R_EBP], 1 << d_ot); + + gen_op_mov_reg_v(d_ot, R_EBP, cpu_T[0]); + gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]); +} + static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) { gen_update_cc_op(s); @@ -5141,20 +5155,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } break; case 0xc9: /* leave */ - /* XXX: exception not precise (ESP is updated before potential exception) */ - if (CODE64(s)) { - gen_op_mov_TN_reg(MO_64, 0, R_EBP); - gen_op_mov_reg_T0(MO_64, R_ESP); - } else if (s->ss32) { - gen_op_mov_TN_reg(MO_32, 0, R_EBP); - gen_op_mov_reg_T0(MO_32, R_ESP); - } else { - gen_op_mov_TN_reg(MO_16, 0, R_EBP); - gen_op_mov_reg_T0(MO_16, R_ESP); - } - ot = gen_pop_T0(s); - gen_op_mov_reg_T0(ot, R_EBP); - gen_pop_update(s, ot); + gen_leave(s); break; case 0x06: /* push es */ case 0x0e: /* push cs */ -- 1.8.3.1