From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE5M-0000cr-OE for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeE5G-0006av-Ts for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:36 -0500 Received: from mail-pb0-x22c.google.com ([2607:f8b0:400e:c01::22c]:40040) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeE5G-0006ai-MY for qemu-devel@nongnu.org; Wed, 06 Nov 2013 20:08:30 -0500 Received: by mail-pb0-f44.google.com with SMTP id rp8so310695pbb.17 for ; Wed, 06 Nov 2013 17:08:29 -0800 (PST) Received: from pebble.com (CPE-138-130-249-46.lnse4.cha.bigpond.net.au. [138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.08.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:08:29 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 7 Nov 2013 11:05:20 +1000 Message-Id: <1383786324-18415-58-git-send-email-rth@twiddle.net> In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-1.8 57/61] target-i386: Tidy gen_add_A0_im List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im and clean up the ifdef. Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im. Signed-off-by: Richard Henderson --- target-i386/translate.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 0b49a35..f8290b3 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -376,29 +376,12 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg) } } -static inline void gen_op_addl_A0_im(int32_t val) -{ - tcg_gen_addi_tl(cpu_A0, cpu_A0, val); -#ifdef TARGET_X86_64 - tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); -#endif -} - -#ifdef TARGET_X86_64 -static inline void gen_op_addq_A0_im(int64_t val) -{ - tcg_gen_addi_tl(cpu_A0, cpu_A0, val); -} -#endif - static void gen_add_A0_im(DisasContext *s, int val) { -#ifdef TARGET_X86_64 - if (CODE64(s)) - gen_op_addq_A0_im(val); - else -#endif - gen_op_addl_A0_im(val); + tcg_gen_addi_tl(cpu_A0, cpu_A0, val); + if (!CODE64(s)) { + tcg_gen_ext32u_tl(cpu_A0, cpu_A0); + } } static inline void gen_op_jmp_T0(void) @@ -6233,7 +6216,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, exception */ gen_op_jmp_T0(); /* pop selector */ - gen_op_addl_A0_im(1 << dflag); + gen_add_A0_im(s, 1 << dflag); gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0); gen_op_movl_seg_T0_vm(R_CS); /* add stack offset */ -- 1.8.3.1