From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Viecb-0008Mt-Uw for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ViecV-0004kQ-Vs for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:13 -0500 Received: from mail-pd0-f182.google.com ([209.85.192.182]:50691) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViecV-0004kG-Pm for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:07 -0500 Received: by mail-pd0-f182.google.com with SMTP id v10so2078361pde.27 for ; Mon, 18 Nov 2013 22:17:07 -0800 (PST) From: Christoffer Dall Date: Mon, 18 Nov 2013 22:18:08 -0800 Message-Id: <1384841896-19566-3-git-send-email-christoffer.dall@linaro.org> In-Reply-To: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> References: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> Subject: [Qemu-devel] [RFC PATCH v3 02/10] hw: arm_gic: Introduce gic_set_priority function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: Peter Maydell Signed-off-by: Christoffer Dall --- hw/intc/arm_gic.c | 15 ++++++++++----- hw/intc/gic_internal.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index c7a24d5..7eaa55f 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -169,6 +169,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu) return new_irq; } +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val) +{ + if (irq < GIC_INTERNAL) { + s->priority1[irq][cpu] = val; + } else { + s->priority2[(irq) - GIC_INTERNAL] = val; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -444,11 +453,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x400) + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < GIC_INTERNAL) { - s->priority1[irq][cpu] = value; - } else { - s->priority2[irq - GIC_INTERNAL] = value; - } + gic_set_priority(s, cpu, irq, value); } else if (offset < 0xc00) { /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the * annoying exception of the 11MPCore's GIC. diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 3989fd1..f916725 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -61,5 +61,6 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu); void gic_complete_irq(GICState *s, int cpu, int irq); void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s, int num_irq); +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); #endif /* !QEMU_ARM_GIC_INTERNAL_H */ -- 1.8.4.3