From: Jia Liu <proljc@gmail.com>
To: qemu-devel@nongnu.org
Cc: blauwirbel@gmail.com, sebastian@macke.de, aliguori@amazon.com
Subject: [Qemu-devel] [PULL 2/7] target-openrisc: Remove unnecessary code generated by jump instructions
Date: Wed, 20 Nov 2013 22:38:33 +0800 [thread overview]
Message-ID: <1384958318-9145-3-git-send-email-proljc@gmail.com> (raw)
In-Reply-To: <1384958318-9145-1-git-send-email-proljc@gmail.com>
From: Sebastian Macke <sebastian@macke.de>
The sr_f variable is only used for the l.bf and l.bnf instructions.
For clarity the code is also rewritten using a switch statement instead
of if chaining.
Signed-off-by: Sebastian Macke <sebastian@macke.de>
Reviewed-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Jia Liu <proljc@gmail.com>
---
target-openrisc/translate.c | 45 ++++++++++++++++++++++++++-------------------
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 8276ce7..91c60eb 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -209,42 +209,49 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
{
target_ulong tmp_pc;
- int lab = gen_new_label();
- TCGv sr_f = tcg_temp_new();
/* N26, 26bits imm */
tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
- tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
- if (op0 == 0x00) { /* l.j */
+ switch (op0) {
+ case 0x00: /* l.j */
tcg_gen_movi_tl(jmp_pc, tmp_pc);
- } else if (op0 == 0x01) { /* l.jal */
+ break;
+ case 0x01: /* l.jal */
tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
tcg_gen_movi_tl(jmp_pc, tmp_pc);
- } else if (op0 == 0x03) { /* l.bnf */
- tcg_gen_movi_tl(jmp_pc, dc->pc+8);
- tcg_gen_brcondi_i32(TCG_COND_EQ, sr_f, SR_F, lab);
- tcg_gen_movi_tl(jmp_pc, tmp_pc);
- gen_set_label(lab);
- } else if (op0 == 0x04) { /* l.bf */
- tcg_gen_movi_tl(jmp_pc, dc->pc+8);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_f, SR_F, lab);
- tcg_gen_movi_tl(jmp_pc, tmp_pc);
- gen_set_label(lab);
- } else if (op0 == 0x11) { /* l.jr */
+ break;
+ case 0x03: /* l.bnf */
+ case 0x04: /* l.bf */
+ {
+ int lab = gen_new_label();
+ TCGv sr_f = tcg_temp_new();
+ tcg_gen_movi_tl(jmp_pc, dc->pc+8);
+ tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
+ tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
+ sr_f, SR_F, lab);
+ tcg_gen_movi_tl(jmp_pc, tmp_pc);
+ gen_set_label(lab);
+ tcg_temp_free(sr_f);
+ }
+ break;
+ case 0x11: /* l.jr */
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
- } else if (op0 == 0x12) { /* l.jalr */
+ break;
+ case 0x12: /* l.jalr */
tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
- } else {
+ break;
+ default:
gen_illegal_exception(dc);
+ break;
}
- tcg_temp_free(sr_f);
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
gen_sync_flags(dc);
}
+
static void dec_calc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1, op2;
--
1.8.3.4 (Apple Git-47)
next prev parent reply other threads:[~2013-11-20 14:39 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-20 14:38 [Qemu-devel] [PULL 0/7] OpenRISC patch queue for 1.7 Jia Liu
2013-11-20 14:38 ` [Qemu-devel] [PULL 1/7] target-openrisc: Speed up move instruction Jia Liu
2013-11-20 14:38 ` Jia Liu [this message]
2013-11-20 14:38 ` [Qemu-devel] [PULL 3/7] target-openrisc: Remove executable flag for every page Jia Liu
2013-11-20 14:38 ` [Qemu-devel] [PULL 4/7] target-openrisc: Correct wrong epcr register in interrupt handler Jia Liu
2013-11-20 14:38 ` [Qemu-devel] [PULL 5/7] openrisc-timer: Reduce overhead, Separate clock update functions Jia Liu
2013-11-20 14:38 ` [Qemu-devel] [PULL 6/7] target-openrisc: Correct memory bounds checking for the tlb buffers Jia Liu
2013-11-20 14:38 ` [Qemu-devel] [PULL 7/7] target-openrisc: Correct carry flag check of l.addc and l.addic test cases Jia Liu
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