From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50187) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VjuMH-00008h-8o for qemu-devel@nongnu.org; Fri, 22 Nov 2013 12:17:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VjuMF-0001vd-S3 for qemu-devel@nongnu.org; Fri, 22 Nov 2013 12:17:33 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:42837 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VjuMF-0001rX-Ko for qemu-devel@nongnu.org; Fri, 22 Nov 2013 12:17:31 -0500 From: Peter Maydell Date: Fri, 22 Nov 2013 17:17:13 +0000 Message-Id: <1385140638-10444-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1385140638-10444-1-git-send-email-peter.maydell@linaro.org> References: <1385140638-10444-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v9 06/11] target-arm: Allow secondary KVM CPUs to be booted via PSCI List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, patches@linaro.org New ARM boards are generally expected to boot their secondary CPUs via the PSCI interface, rather than ad-hoc "loop around in holding pen code" as hw/arm/boot.c implements. In particular this is necessary for mach-virt kernels. For KVM we achieve this by creating the VCPUs with a feature flag marking them as starting in PSCI powered-down state; the guest kernel will then make a PSCI call (implemented in the host kernel) to start the secondaries at an address of its choosing once it has got the primary CPU up. Implement this setting of the feature flag, controlled by a qdev property for ARMCPU, which board code can set if it is a PSCI system. Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 3 +++ target-arm/cpu.c | 7 +++++++ target-arm/kvm.c | 3 +++ 3 files changed, 13 insertions(+) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index cbb9eec..8bd3e36 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -94,6 +94,9 @@ typedef struct ARMCPU { /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; + /* Should CPU start in PSCI powered-off state? */ + bool start_powered_off; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4c8d9c7..0325815 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "qemu-common.h" +#include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif @@ -944,6 +945,11 @@ static const ARMCPUInfo arm_cpus[] = { #endif }; +static Property arm_cpu_properties[] = { + DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), + DEFINE_PROP_END_OF_LIST() +}; + static void arm_cpu_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc = ARM_CPU_CLASS(oc); @@ -952,6 +958,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) acc->parent_realize = dc->realize; dc->realize = arm_cpu_realizefn; + dc->props = arm_cpu_properties; acc->parent_reset = cc->reset; cc->reset = arm_cpu_reset; diff --git a/target-arm/kvm.c b/target-arm/kvm.c index 3098456..80c58c5 100644 --- a/target-arm/kvm.c +++ b/target-arm/kvm.c @@ -79,6 +79,9 @@ int kvm_arch_init_vcpu(CPUState *cs) init.target = KVM_ARM_TARGET_CORTEX_A15; memset(init.features, 0, sizeof(init.features)); + if (cpu->start_powered_off) { + init.features[0] = 1 << KVM_ARM_VCPU_POWER_OFF; + } ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); if (ret) { return ret; -- 1.7.9.5