From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VlGOG-0000Mh-Oy for qemu-devel@nongnu.org; Tue, 26 Nov 2013 06:01:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VlGOA-0008Sw-LG for qemu-devel@nongnu.org; Tue, 26 Nov 2013 06:01:12 -0500 Received: from mx1.redhat.com ([209.132.183.28]:62034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VlGOA-0008Rz-Da for qemu-devel@nongnu.org; Tue, 26 Nov 2013 06:01:06 -0500 Message-ID: <1385463651.10163.10.camel@nilsson.home.kraxel.org> From: Gerd Hoffmann Date: Tue, 26 Nov 2013 12:00:51 +0100 In-Reply-To: <20131126091014.GA18777@redhat.com> References: <1384775449-6693-1-git-send-email-mst@redhat.com> <1384775449-6693-2-git-send-email-mst@redhat.com> <52945802.2010309@redhat.com> <20131126091014.GA18777@redhat.com> Content-Type: multipart/mixed; boundary="=-BJL1hreL5ROwK4dSdkiQ" Mime-Version: 1.0 Subject: Re: [Qemu-devel] [PULL for-1.8 1/2] pc: disable pci-info List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Eduardo Habkost , "Jordan Justen (Intel address)" , qemu-devel@nongnu.org, Anthony Liguori , Igor Mammedov , Laszlo Ersek --=-BJL1hreL5ROwK4dSdkiQ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Hi, > I think it's down to other qemu bugs (such as _CRS not covering > all of PCI memory), we shall just fix them. i.e. the attached patch should fixup things. cheers, Gerd --=-BJL1hreL5ROwK4dSdkiQ Content-Type: text/x-patch; name="0001-piix-fix-32bit-pci-hole.patch"; charset="UTF-8" Content-Description: Content-Disposition: inline; filename="0001-piix-fix-32bit-pci-hole.patch" Content-Transfer-Encoding: 7bit >>From a81b8d66e24fd298ce7654d424a378337e6cf132 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 26 Nov 2013 11:46:11 +0100 Subject: [PATCH] piix: fix 32bit pci hole Make the 32bit pci hole start at end of ram, so all possible address space is covered. Of course the firmware can use less than that. Leaving space unused is no problem, mapping pci bars outside the hole causes problems though. Signed-off-by: Gerd Hoffmann --- hw/pci-host/piix.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index edc974e..1414a2b 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -345,15 +345,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, f->ram_memory = ram_memory; i440fx = I440FX_PCI_HOST_BRIDGE(dev); - /* Set PCI window size the way seabios has always done it. */ - /* Power of 2 so bios can cover it with a single MTRR */ - if (ram_size <= 0x80000000) { - i440fx->pci_info.w32.begin = 0x80000000; - } else if (ram_size <= 0xc0000000) { - i440fx->pci_info.w32.begin = 0xc0000000; - } else { - i440fx->pci_info.w32.begin = 0xe0000000; - } + i440fx->pci_info.w32.begin = ram_size; memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space, pci_hole_start, pci_hole_size); -- 1.8.3.1 --=-BJL1hreL5ROwK4dSdkiQ--