From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VlKS0-0001Jy-3A for qemu-devel@nongnu.org; Tue, 26 Nov 2013 10:21:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VlKRs-00072s-BC for qemu-devel@nongnu.org; Tue, 26 Nov 2013 10:21:20 -0500 Received: from mx1.redhat.com ([209.132.183.28]:54040) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VlKRs-00072m-3g for qemu-devel@nongnu.org; Tue, 26 Nov 2013 10:21:12 -0500 Message-ID: <1385479258.10163.13.camel@nilsson.home.kraxel.org> From: Gerd Hoffmann Date: Tue, 26 Nov 2013 16:20:58 +0100 In-Reply-To: <20131126140455.GD21803@redhat.com> References: <1384775449-6693-1-git-send-email-mst@redhat.com> <1384775449-6693-2-git-send-email-mst@redhat.com> <52945802.2010309@redhat.com> <20131126091014.GA18777@redhat.com> <1385463651.10163.10.camel@nilsson.home.kraxel.org> <20131126140455.GD21803@redhat.com> Content-Type: multipart/mixed; boundary="=-tAMtmN5S2jPreNWzwJZh" Mime-Version: 1.0 Subject: Re: [Qemu-devel] [PULL for-1.8 1/2] pc: disable pci-info List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Eduardo Habkost , "Jordan Justen (Intel address)" , qemu-devel@nongnu.org, Anthony Liguori , Igor Mammedov , Laszlo Ersek --=-tAMtmN5S2jPreNWzwJZh Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit On Di, 2013-11-26 at 16:04 +0200, Michael S. Tsirkin wrote: > On Tue, Nov 26, 2013 at 12:00:51PM +0100, Gerd Hoffmann wrote: > > Hi, > > > > > I think it's down to other qemu bugs (such as _CRS not covering > > > all of PCI memory), we shall just fix them. > > > > i.e. the attached patch should fixup things. > > > > cheers, > > Gerd > > > > Yes, I think it's a start. Q35 is a bit harder because of the MMIO > region. ??? Do you mean mmconfig? That can live inside the window. So something like the attached patch should work in theory. In practice it hasn't the expected effect for some reason ... > Do we want to tweak end too? There's all kind of > stuff there so need to be careful ... I'd leave the end as-is, at the ioapic address. cheers, Gerd --=-tAMtmN5S2jPreNWzwJZh Content-Description: Content-Disposition: inline; filename="0001-wip-q35-fix-32bit-pci-hole.patch" Content-Type: text/x-patch; name="0001-wip-q35-fix-32bit-pci-hole.patch"; charset="UTF-8" Content-Transfer-Encoding: 7bit >>From 3d01b6c46fbf655bdb9b4f7ca427f40959b05d31 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 26 Nov 2013 16:18:04 +0100 Subject: [PATCH] [wip] q35: fix 32bit pci hole Signed-off-by: Gerd Hoffmann --- hw/pci-host/q35.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index c043998..8d47bf9 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -179,15 +179,6 @@ static void q35_host_initfn(Object *obj) object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", q35_host_get_mmcfg_size, NULL, NULL, NULL, NULL); - - /* Leave enough space for the biggest MCFG BAR */ - /* TODO: this matches current bios behaviour, but - * it's not a power of two, which means an MTRR - * can't cover it exactly. - */ - s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + - MCH_HOST_BRIDGE_PCIEXBAR_MAX; - s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; } static const TypeInfo q35_host_info = { @@ -365,6 +356,8 @@ static int mch_init(PCIDevice *d) 0x100000000ULL - mch->below_4g_mem_size); memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, &mch->pci_hole); + mch->pci_info.w32.begin = mch->below_4g_mem_size; + mch->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size); pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size, -- 1.8.3.1 --=-tAMtmN5S2jPreNWzwJZh--