From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmELO-0002ia-E5 for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmELH-00027Y-5X for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:14 -0500 Received: from mail-pb0-x22b.google.com ([2607:f8b0:400e:c01::22b]:64255) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmELG-00025X-Qg for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:07 -0500 Received: by mail-pb0-f43.google.com with SMTP id rq2so13579346pbb.16 for ; Thu, 28 Nov 2013 19:02:05 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.02.02 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:02:05 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Fri, 29 Nov 2013 16:00:01 +1300 Message-Id: <1385694047-6116-15-git-send-email-rth@twiddle.net> In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 14/60] target-i386: Fix typo in gen_push_T1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org By inspection, obviously we should be storing T[1] not T[0]. This could only happen for x86_64 in 64-bit mode with 0x66 prefix to call insn -- i.e. never. Signed-off-by: Richard Henderson --- target-i386/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index b28663b..c1591d9 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2487,7 +2487,7 @@ static void gen_push_T1(DisasContext *s) gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0); } else { gen_op_addq_A0_im(-2); - gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); + gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0); } gen_op_mov_reg_A0(2, R_ESP); } else -- 1.8.3.1