From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40267) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmELt-0003fS-GV for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmELn-0002Le-5Q for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:45 -0500 Received: from mail-pb0-x232.google.com ([2607:f8b0:400e:c01::232]:47222) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmELm-0002KT-Pq for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:39 -0500 Received: by mail-pb0-f50.google.com with SMTP id rr13so13477097pbb.23 for ; Thu, 28 Nov 2013 19:02:37 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.02.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:02:37 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Fri, 29 Nov 2013 16:00:07 +1300 Message-Id: <1385694047-6116-21-git-send-email-rth@twiddle.net> In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 20/60] target-i386: Tidy load + truncate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org We can now use tcg_gen_qemu_ld_i32 directly to avoid the truncation. Signed-off-by: Richard Henderson --- target-i386/translate.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 16fae82..117714d 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4302,12 +4302,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x22: if (ot == MO_32) { /* pinsrd */ if (mod == 3) { - gen_op_mov_v_reg(ot, cpu_tmp0, rm); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[rm]); } else { - tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0, - s->mem_index, MO_LEUL); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); } - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, xmm_regs[reg].XMM_L(val & 3))); @@ -5904,13 +5903,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch(op >> 4) { case 0: - gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32); break; case 1: - gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); break; case 2: @@ -5920,8 +5919,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 3: default: - gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LESW); gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); break; } @@ -5943,13 +5942,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0: switch(op >> 4) { case 0: - gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32); break; case 1: - gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); break; case 2: @@ -5959,8 +5958,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 3: default: - gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LESW); gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); break; } @@ -6022,8 +6021,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); break; case 0x0d: /* fldcw mem */ - gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUW); gen_helper_fldcw(cpu_env, cpu_tmp2_i32); break; case 0x0e: /* fnstenv mem */ @@ -7951,8 +7950,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, goto illegal_op; gen_lea_modrm(env, s, modrm); if (op == 2) { - gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); } else { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); -- 1.8.3.1