From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40379) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEM7-00041y-SQ for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmEM1-0002V4-Uu for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:59 -0500 Received: from mail-pb0-x22a.google.com ([2607:f8b0:400e:c01::22a]:37226) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEM1-0002UJ-BZ for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:53 -0500 Received: by mail-pb0-f42.google.com with SMTP id uo5so13595276pbc.15 for ; Thu, 28 Nov 2013 19:02:52 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.02.49 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:02:51 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Fri, 29 Nov 2013 16:00:11 +1300 Message-Id: <1385694047-6116-25-git-send-email-rth@twiddle.net> In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 24/60] target-i386: Remove gen_op_movl_T0_im* List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Propagate the definition of gen_op_movl_T0_im to all users. The function gen_op_movl_T0_imu was unused. Signed-off-by: Richard Henderson --- target-i386/translate.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 6f88ed9..d836aee 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_movl_T0_im(int32_t val) -{ - tcg_gen_movi_tl(cpu_T[0], val); -} - -static inline void gen_op_movl_T0_imu(uint32_t val) -{ - tcg_gen_movi_tl(cpu_T[0], val); -} - static inline void gen_op_movl_T1_im(int32_t val) { tcg_gen_movi_tl(cpu_T[1], val); @@ -3499,13 +3489,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } val = cpu_ldub_code(env, s->pc++); if (is_xmm) { - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); op1_offset = offsetof(CPUX86State,xmm_t0); } else { - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); @@ -5379,7 +5369,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, val = insn_get(env, s, ot); else val = (int8_t)insn_get(env, s, MO_8); - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); gen_push_T0(s); break; case 0x8f: /* pop Ev */ @@ -5508,7 +5498,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_lea_modrm(env, s, modrm); } val = insn_get(env, s, ot); - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); if (mod != 3) { gen_op_st_v(s, ot, cpu_T[0], cpu_A0); } else { @@ -5684,7 +5674,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 0xb0 ... 0xb7: /* mov R, Ib */ val = insn_get(env, s, MO_8); - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s)); break; case 0xb8 ... 0xbf: /* mov R, Iv */ @@ -5703,7 +5693,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = dflag ? MO_32 : MO_16; val = insn_get(env, s, ot); reg = (b & 7) | REX_B(s); - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); gen_op_mov_reg_T0(ot, reg); } break; @@ -6507,12 +6497,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, else ot = dflag ? MO_32 : MO_16; val = cpu_ldub_code(env, s->pc++); - gen_op_movl_T0_im(val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); if (use_icount) gen_io_start(); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); gen_op_mov_reg_T1(ot, R_EAX); if (use_icount) { @@ -6527,14 +6516,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, else ot = dflag ? MO_32 : MO_16; val = cpu_ldub_code(env, s->pc++); - gen_op_movl_T0_im(val); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); gen_op_mov_TN_reg(ot, 1, R_EAX); if (use_icount) gen_io_start(); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); if (use_icount) { @@ -6686,7 +6674,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, offset = insn_get(env, s, ot); selector = insn_get(env, s, MO_16); - gen_op_movl_T0_im(selector); + tcg_gen_movi_tl(cpu_T[0], selector); gen_op_movl_T1_imu(offset); } goto do_lcall; @@ -6712,7 +6700,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, offset = insn_get(env, s, ot); selector = insn_get(env, s, MO_16); - gen_op_movl_T0_im(selector); + tcg_gen_movi_tl(cpu_T[0], selector); gen_op_movl_T1_imu(offset); } goto do_ljmp; -- 1.8.3.1