From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEMM-0004SE-2y for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmEMF-0002d2-SZ for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:14 -0500 Received: from mail-pd0-x22a.google.com ([2607:f8b0:400e:c02::22a]:45839) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEMF-0002cI-Hm for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:07 -0500 Received: by mail-pd0-f170.google.com with SMTP id g10so12990945pdj.15 for ; Thu, 28 Nov 2013 19:03:06 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.03.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:03:05 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Fri, 29 Nov 2013 16:00:15 +1300 Message-Id: <1385694047-6116-29-git-send-email-rth@twiddle.net> In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 28/60] target-i386: Remove gen_op_andl_T0_ffff List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Replace it with tcg_gen_ext16u_tl. In four places we can combine that with a previous move into cpu_T[0], and in one place we can infer that the zero-extension has already happened via the previous load. Signed-off-by: Richard Henderson --- target-i386/translate.c | 43 ++++++++++++++++++------------------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 58bea41..236d0a7 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_andl_T0_ffff(void) -{ - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); -} - static inline void gen_op_andl_T0_im(uint32_t val) { tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); @@ -5006,8 +5001,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 2: /* call Ev */ /* XXX: optimize if memory (no 'and' is necessary) */ - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + if (s->dflag == 0) { + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + } next_eip = s->pc - s->cs_base; tcg_gen_movi_tl(cpu_T[1], next_eip); gen_push_T1(s); @@ -5035,8 +5031,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_eob(s); break; case 4: /* jmp Ev */ - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + if (s->dflag == 0) { + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + } gen_op_jmp_T0(); gen_eob(s); break; @@ -6421,8 +6418,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = MO_8; else ot = dflag ? MO_32 : MO_16; - gen_op_mov_TN_reg(MO_16, 0, R_EDX); - gen_op_andl_T0_ffff(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { @@ -6440,8 +6436,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = MO_8; else ot = dflag ? MO_32 : MO_16; - gen_op_mov_TN_reg(MO_16, 0, R_EDX); - gen_op_andl_T0_ffff(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes) | 4); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { @@ -6503,8 +6498,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = MO_8; else ot = dflag ? MO_32 : MO_16; - gen_op_mov_TN_reg(MO_16, 0, R_EDX); - gen_op_andl_T0_ffff(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); if (use_icount) @@ -6523,8 +6517,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = MO_8; else ot = dflag ? MO_32 : MO_16; - gen_op_mov_TN_reg(MO_16, 0, R_EDX); - gen_op_andl_T0_ffff(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); gen_op_mov_TN_reg(ot, 1, R_EAX); @@ -6549,16 +6542,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (CODE64(s) && s->dflag) s->dflag = 2; gen_stack_update(s, val + (2 << s->dflag)); - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + if (s->dflag == 0) { + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + } gen_op_jmp_T0(); gen_eob(s); break; case 0xc3: /* ret */ gen_pop_T0(s); gen_pop_update(s); - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + if (s->dflag == 0) { + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + } gen_op_jmp_T0(); gen_eob(s); break; @@ -6574,15 +6569,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_stack_A0(s); /* pop offset */ - gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0); - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0); /* NOTE: keeping EIP updated is not a problem in case of exception */ gen_op_jmp_T0(); /* pop selector */ gen_op_addl_A0_im(2 << s->dflag); - gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0); + gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0); gen_op_movl_seg_T0_vm(R_CS); /* add stack offset */ gen_stack_update(s, val + (4 << s->dflag)); -- 1.8.3.1