From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEMP-0004Yf-Fz for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmEMJ-0002e3-2D for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:17 -0500 Received: from mail-pb0-x234.google.com ([2607:f8b0:400e:c01::234]:65533) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEMI-0002dr-SJ for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:11 -0500 Received: by mail-pb0-f52.google.com with SMTP id uo5so13548983pbc.39 for ; Thu, 28 Nov 2013 19:03:10 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.03.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:03:09 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Fri, 29 Nov 2013 16:00:16 +1300 Message-Id: <1385694047-6116-30-git-send-email-rth@twiddle.net> In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 29/60] target-i386: Remove gen_op_andl_T0_im List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Replace it with its definition. Signed-off-by: Richard Henderson --- target-i386/translate.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 236d0a7..009529e 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_andl_T0_im(uint32_t val) -{ - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); -} - static inline void gen_op_movl_T0_T1(void) { tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); @@ -7362,8 +7357,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); gen_add_A0_im(s, 2); tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); - if (!s->dflag) - gen_op_andl_T0_im(0xffffff); + if (s->dflag == 0) { + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); + } gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); break; case 1: @@ -7425,8 +7421,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); gen_add_A0_im(s, 2); tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); - if (!s->dflag) - gen_op_andl_T0_im(0xffffff); + if (s->dflag == 0) { + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); + } gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); } break; @@ -7525,8 +7522,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0); gen_add_A0_im(s, 2); gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); - if (!s->dflag) - gen_op_andl_T0_im(0xffffff); + if (s->dflag == 0) { + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff); + } if (op == 2) { tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); -- 1.8.3.1