From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40593) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEMX-0004mo-48 for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmEMR-0002i9-9I for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:25 -0500 Received: from mail-pd0-x22d.google.com ([2607:f8b0:400e:c02::22d]:39652) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEMQ-0002hL-QH for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:03:19 -0500 Received: by mail-pd0-f173.google.com with SMTP id p10so12997703pdj.32 for ; Thu, 28 Nov 2013 19:03:18 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.03.13 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:03:17 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Fri, 29 Nov 2013 16:00:18 +1300 Message-Id: <1385694047-6116-32-git-send-email-rth@twiddle.net> In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 31/60] target-i386: Remove gen_op_andl_A0_ffff List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Replace it with tcg_gen_ext16u_tl, and in two cases merge with a previous move from cpu_regs. Signed-off-by: Richard Henderson --- target-i386/translate.c | 33 +++++++++++++-------------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index bb45c2b..e075fe3 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_andl_A0_ffff(void) -{ - tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); -} - #ifdef TARGET_X86_64 #define NB_OP_SIZES 4 @@ -568,8 +563,7 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s) /* 16 address, always override */ if (override < 0) override = R_DS; - gen_op_movl_A0_reg(R_ESI); - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]); gen_op_addl_A0_seg(s, override); } } @@ -589,8 +583,7 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s) gen_op_movl_A0_reg(R_EDI); } } else { - gen_op_movl_A0_reg(R_EDI); - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]); gen_op_addl_A0_seg(s, R_ES); } } @@ -2058,7 +2051,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm) } if (disp != 0) gen_op_addl_A0_im(disp); - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); no_rm: if (must_add_seg) { if (override < 0) { @@ -2391,7 +2384,7 @@ static void gen_push_T0(DisasContext *s) gen_op_addl_A0_seg(s, R_SS); } } else { - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); gen_op_addl_A0_seg(s, R_SS); } @@ -2431,7 +2424,7 @@ static void gen_push_T1(DisasContext *s) gen_op_addl_A0_seg(s, R_SS); } } else { - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); gen_op_addl_A0_seg(s, R_SS); } gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0); @@ -2458,7 +2451,7 @@ static void gen_pop_T0(DisasContext *s) if (s->addseg) gen_op_addl_A0_seg(s, R_SS); } else { - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); gen_op_addl_A0_seg(s, R_SS); } gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0); @@ -2481,7 +2474,7 @@ static void gen_stack_A0(DisasContext *s) { gen_op_movl_A0_reg(R_ESP); if (!s->ss32) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); if (s->addseg) gen_op_addl_A0_seg(s, R_SS); @@ -2494,7 +2487,7 @@ static void gen_pusha(DisasContext *s) gen_op_movl_A0_reg(R_ESP); gen_op_addl_A0_im(-16 << s->dflag); if (!s->ss32) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); if (s->addseg) gen_op_addl_A0_seg(s, R_SS); @@ -2512,7 +2505,7 @@ static void gen_popa(DisasContext *s) int i; gen_op_movl_A0_reg(R_ESP); if (!s->ss32) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); if (s->addseg) @@ -2563,7 +2556,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_op_movl_A0_reg(R_ESP); gen_op_addl_A0_im(-opsize); if (!s->ss32) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); tcg_gen_mov_tl(cpu_T[1], cpu_A0); if (s->addseg) gen_op_addl_A0_seg(s, R_SS); @@ -4423,7 +4416,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, { gen_op_movl_A0_reg(R_EDI); if (s->aflag == 0) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); } gen_add_A0_ds_seg(s); @@ -5618,7 +5611,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); if (s->aflag == 0) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); else tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); } @@ -7374,7 +7367,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, { gen_op_movl_A0_reg(R_EAX); if (s->aflag == 0) - gen_op_andl_A0_ffff(); + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); } gen_add_A0_ds_seg(s); gen_helper_monitor(cpu_env, cpu_A0); -- 1.8.3.1