* [Qemu-devel] [PATCH v2 01/60] exec: Delay CPU_LOG_TB_CPU until we actually execute a TB
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 02/60] target-i386: Push DisasContext into load/store helpers Richard Henderson
` (59 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
The previous placement could result in duplicate logging while
still processing interrupts.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
cpu-exec.c | 36 +++++++++++++++++++-----------------
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 30cfa2a..3c4800f 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -53,7 +53,25 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc)
static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
{
CPUArchState *env = cpu->env_ptr;
- uintptr_t next_tb = tcg_qemu_tb_exec(env, tb_ptr);
+ uintptr_t next_tb;
+
+#if defined(DEBUG_DISAS)
+ if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
+#if defined(TARGET_I386)
+ log_cpu_state(cpu, CPU_DUMP_CCOP);
+#elif defined(TARGET_M68K)
+ /* ??? Should not modify env state for dumping. */
+ cpu_m68k_flush_flags(env, env->cc_op);
+ env->cc_op = CC_OP_FLAGS;
+ env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
+ log_cpu_state(cpu, 0);
+#else
+ log_cpu_state(cpu, 0);
+#endif
+ }
+#endif /* DEBUG_DISAS */
+
+ next_tb = tcg_qemu_tb_exec(env, tb_ptr);
if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
/* We didn't start executing this TB (eg because the instruction
* counter hit zero); we must restore the guest PC to the address
@@ -579,22 +597,6 @@ int cpu_exec(CPUArchState *env)
env->exception_index = EXCP_INTERRUPT;
cpu_loop_exit(env);
}
-#if defined(DEBUG_DISAS)
- if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
- /* restore flags in standard format */
-#if defined(TARGET_I386)
- log_cpu_state(cpu, CPU_DUMP_CCOP);
-#elif defined(TARGET_M68K)
- cpu_m68k_flush_flags(env, env->cc_op);
- env->cc_op = CC_OP_FLAGS;
- env->sr = (env->sr & 0xffe0)
- | env->cc_dest | (env->cc_x << 4);
- log_cpu_state(cpu, 0);
-#else
- log_cpu_state(cpu, 0);
-#endif
- }
-#endif /* DEBUG_DISAS */
spin_lock(&tcg_ctx.tb_ctx.tb_lock);
tb = tb_find_fast(env);
/* Note: we do it here to avoid a gcc bug on Mac OS X when
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 02/60] target-i386: Push DisasContext into load/store helpers
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 01/60] exec: Delay CPU_LOG_TB_CPU until we actually execute a TB Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 03/60] target-i386: Stop encoding DisasContext.mem_index Richard Henderson
` (58 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
Rather than add s->mem_index into a combined size+mem_index
argument, pass the context down. This will allow cleaning
up s->mem_index later.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 331 +++++++++++++++++++++++++-----------------------
1 file changed, 170 insertions(+), 161 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7916e5b..8c5c16b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -584,9 +584,9 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
}
#endif
-static inline void gen_op_lds_T0_A0(int idx)
+static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
@@ -601,9 +601,9 @@ static inline void gen_op_lds_T0_A0(int idx)
}
}
-static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
+static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8u(t0, a0, mem_index);
@@ -625,24 +625,24 @@ static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
}
/* XXX: always use ldu or lds */
-static inline void gen_op_ld_T0_A0(int idx)
+static inline void gen_op_ld_T0_A0(DisasContext *s, int idx)
{
- gen_op_ld_v(idx, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
}
-static inline void gen_op_ldu_T0_A0(int idx)
+static inline void gen_op_ldu_T0_A0(DisasContext *s, int idx)
{
- gen_op_ld_v(idx, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
}
-static inline void gen_op_ld_T1_A0(int idx)
+static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
{
- gen_op_ld_v(idx, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, idx, cpu_T[1], cpu_A0);
}
-static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
+static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_st8(t0, a0, mem_index);
@@ -663,14 +663,14 @@ static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
}
}
-static inline void gen_op_st_T0_A0(int idx)
+static inline void gen_op_st_T0_A0(DisasContext *s, int idx)
{
- gen_op_st_v(idx, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
}
-static inline void gen_op_st_T1_A0(int idx)
+static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
{
- gen_op_st_v(idx, cpu_T[1], cpu_A0);
+ gen_op_st_v(s, idx, cpu_T[1], cpu_A0);
}
static inline void gen_jmp_im(target_ulong pc)
@@ -867,9 +867,9 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
static inline void gen_movs(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
gen_string_movl_A0_EDI(s);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1294,7 +1294,7 @@ static inline void gen_stos(DisasContext *s, int ot)
{
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
gen_string_movl_A0_EDI(s);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
@@ -1302,7 +1302,7 @@ static inline void gen_stos(DisasContext *s, int ot)
static inline void gen_lods(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
@@ -1311,7 +1311,7 @@ static inline void gen_lods(DisasContext *s, int ot)
static inline void gen_scas(DisasContext *s, int ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1320,7 +1320,7 @@ static inline void gen_scas(DisasContext *s, int ot)
static inline void gen_cmps(DisasContext *s, int ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
@@ -1336,12 +1336,12 @@ static inline void gen_ins(DisasContext *s, int ot)
/* Note: we must do this dummy write first to be restartable in
case of page fault. */
gen_op_movl_T0_0();
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
if (use_icount)
@@ -1353,7 +1353,7 @@ static inline void gen_outs(DisasContext *s, int ot)
if (use_icount)
gen_io_start();
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
@@ -1473,7 +1473,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
} else {
- gen_op_ld_T0_A0(ot + s1->mem_index);
+ gen_op_ld_T0_A0(s1, ot);
}
switch(op) {
case OP_ADCL:
@@ -1483,7 +1483,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_ADCB + ot);
break;
@@ -1494,7 +1494,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_SBBB + ot);
break;
@@ -1503,7 +1503,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_ADDB + ot);
break;
@@ -1513,7 +1513,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_SUBB + ot);
break;
@@ -1523,7 +1523,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
@@ -1532,7 +1532,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
@@ -1541,7 +1541,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
@@ -1560,7 +1560,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
if (d != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, d);
else
- gen_op_ld_T0_A0(ot + s1->mem_index);
+ gen_op_ld_T0_A0(s1, ot);
gen_compute_eflags_c(s1, cpu_cc_src);
if (c > 0) {
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
@@ -1572,7 +1572,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
if (d != OR_TMP0)
gen_op_mov_reg_T0(ot, d);
else
- gen_op_st_T0_A0(ot + s1->mem_index);
+ gen_op_st_T0_A0(s1, ot);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
@@ -1628,7 +1628,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1653,7 +1653,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
/* store */
if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, op1);
}
@@ -1668,7 +1668,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
else
gen_op_mov_TN_reg(ot, 0, op1);
@@ -1692,7 +1692,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
/* store */
if (op1 == OR_TMP0)
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
else
gen_op_mov_reg_T0(ot, op1);
@@ -1719,7 +1719,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1760,7 +1760,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
/* store */
if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, op1);
}
@@ -1809,7 +1809,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1855,7 +1855,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
/* store */
if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, op1);
}
@@ -1891,7 +1891,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
else
gen_op_mov_TN_reg(ot, 0, op1);
@@ -1932,7 +1932,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
}
/* store */
if (op1 == OR_TMP0)
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
else
gen_op_mov_reg_T0(ot, op1);
}
@@ -1946,7 +1946,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -2014,7 +2014,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
/* store */
if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, op1);
}
@@ -2363,9 +2363,9 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
if (reg != OR_TMP0)
gen_op_mov_reg_T0(ot, reg);
}
@@ -2566,10 +2566,10 @@ static void gen_push_T0(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T0_A0(OT_QUAD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_QUAD);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2590,7 +2590,7 @@ static void gen_push_T0(DisasContext *s)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
+ gen_op_st_T0_A0(s, s->dflag + 1);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
else
@@ -2607,10 +2607,10 @@ static void gen_push_T1(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T1_A0(OT_QUAD + s->mem_index);
+ gen_op_st_T1_A0(s, OT_QUAD);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2629,7 +2629,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
+ gen_op_st_T1_A0(s, s->dflag + 1);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
@@ -2644,7 +2644,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
+ gen_op_ld_T0_A0(s, s->dflag ? OT_QUAD : OT_WORD);
} else
#endif
{
@@ -2656,7 +2656,7 @@ static void gen_pop_T0(DisasContext *s)
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
+ gen_op_ld_T0_A0(s, s->dflag + 1);
}
}
@@ -2695,7 +2695,7 @@ static void gen_pusha(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
- gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD + s->dflag);
gen_op_addl_A0_im(2 << s->dflag);
}
gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
@@ -2715,7 +2715,7 @@ static void gen_popa(DisasContext *s)
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_WORD + s->dflag);
gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
}
gen_op_addl_A0_im(2 << s->dflag);
@@ -2739,7 +2739,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
/* push bp */
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
if (level) {
/* XXX: must save state */
gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
@@ -2764,7 +2764,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
gen_op_addl_A0_seg(s, R_SS);
/* push bp */
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
if (level) {
/* XXX: must save state */
gen_helper_enter_level(cpu_env, tcg_const_i32(level),
@@ -2846,23 +2846,23 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
gen_jmp_tb(s, eip, 0);
}
-static inline void gen_ldq_env_A0(int idx, int offset)
+static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
}
-static inline void gen_stq_env_A0(int idx, int offset)
+static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
}
-static inline void gen_ldo_env_A0(int idx, int offset)
+static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -2870,9 +2870,9 @@ static inline void gen_ldo_env_A0(int idx, int offset)
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
}
-static inline void gen_sto_env_A0(int idx, int offset)
+static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
- int mem_index = (idx >> 2) - 1;
+ int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -3312,7 +3312,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
+ gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
break;
case 0x1e7: /* movntdq */
case 0x02b: /* movntps */
@@ -3320,13 +3320,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
break;
case 0x3f0: /* lddqu */
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
break;
case 0x22b: /* movntss */
case 0x32b: /* movntsd */
@@ -3334,12 +3334,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (b1 & 1) {
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
- xmm_regs[reg]));
+ gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
}
break;
case 0x6e: /* movd mm, ea */
@@ -3377,7 +3376,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x6f: /* movq mm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
+ gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
@@ -3394,7 +3393,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x26f: /* movdqu xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
@@ -3404,7 +3403,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x210: /* movss xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_movl_T0_0();
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
@@ -3419,7 +3418,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x310: /* movsd xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
gen_op_movl_T0_0();
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
@@ -3433,7 +3433,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x112: /* movlpd */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
/* movhlps */
rm = (modrm & 7) | REX_B(s);
@@ -3444,7 +3445,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x212: /* movsldup */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
@@ -3460,7 +3461,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x312: /* movddup */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
@@ -3473,7 +3475,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x116: /* movhpd */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(1)));
} else {
/* movlhps */
rm = (modrm & 7) | REX_B(s);
@@ -3484,7 +3487,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x216: /* movshdup */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
@@ -3549,7 +3552,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x27e: /* movq xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
@@ -3560,7 +3564,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x7f: /* movq ea, mm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
+ gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
@@ -3575,7 +3579,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x27f: /* movdqu ea, xmm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
+ gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
@@ -3586,7 +3590,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
@@ -3596,7 +3600,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x311: /* movsd ea, xmm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_stq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
@@ -3607,7 +3612,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x113: /* movlpd */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_stq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
goto illegal_op;
}
@@ -3616,7 +3622,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x117: /* movhpd */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
+ gen_stq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(1)));
} else {
goto illegal_op;
}
@@ -3682,7 +3689,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
op2_offset = offsetof(CPUX86State,mmx_t0);
- gen_ldq_env_A0(s->mem_index, op2_offset);
+ gen_ldq_env_A0(s, op2_offset);
} else {
rm = (modrm & 7);
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
@@ -3727,7 +3734,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
op2_offset = offsetof(CPUX86State,xmm_t0);
- gen_ldo_env_A0(s->mem_index, op2_offset);
+ gen_ldo_env_A0(s, op2_offset);
} else {
rm = (modrm & 7) | REX_B(s);
op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
@@ -3758,9 +3765,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if ((b >> 8) & 1) {
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
}
op2_offset = offsetof(CPUX86State,xmm_t0);
@@ -3823,7 +3830,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ gen_stq_env_A0(s, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_Q(0)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
@@ -3894,7 +3902,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
- gen_ldq_env_A0(s->mem_index, op2_offset +
+ gen_ldq_env_A0(s, op2_offset +
offsetof(XMMReg, XMM_Q(0)));
break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
@@ -3912,10 +3920,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(XMMReg, XMM_W(0)));
break;
case 0x2a: /* movntqda */
- gen_ldo_env_A0(s->mem_index, op1_offset);
+ gen_ldo_env_A0(s, op1_offset);
return;
default:
- gen_ldo_env_A0(s->mem_index, op2_offset);
+ gen_ldo_env_A0(s, op2_offset);
}
}
} else {
@@ -3925,7 +3933,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
op2_offset = offsetof(CPUX86State,mmx_t0);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, op2_offset);
+ gen_ldq_env_A0(s, op2_offset);
}
}
if (sse_fn_epp == SSE_SPECIAL) {
@@ -4490,7 +4498,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
op2_offset = offsetof(CPUX86State,xmm_t0);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldo_env_A0(s->mem_index, op2_offset);
+ gen_ldo_env_A0(s, op2_offset);
}
} else {
op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
@@ -4499,7 +4507,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
op2_offset = offsetof(CPUX86State,mmx_t0);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_ldq_env_A0(s->mem_index, op2_offset);
+ gen_ldq_env_A0(s, op2_offset);
}
}
val = cpu_ldub_code(env, s->pc++);
@@ -4572,14 +4580,15 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* specific case for SSE single instructions */
if (b1 == 2) {
/* 32 bit access */
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
} else {
/* 64 bit access */
- gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
+ gen_ldq_env_A0(s, offsetof(CPUX86State,
+ xmm_t0.XMM_D(0)));
}
} else {
- gen_ldo_env_A0(s->mem_index, op2_offset);
+ gen_ldo_env_A0(s, op2_offset);
}
} else {
rm = (modrm & 7) | REX_B(s);
@@ -4590,7 +4599,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
op2_offset = offsetof(CPUX86State,mmx_t0);
- gen_ldq_env_A0(s->mem_index, op2_offset);
+ gen_ldq_env_A0(s, op2_offset);
} else {
rm = (modrm & 7);
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
@@ -4887,7 +4896,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
@@ -4975,7 +4984,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (op == 0)
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -4990,7 +4999,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 2: /* not */
tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
if (mod != 3) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, rm);
}
@@ -4998,7 +5007,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3: /* neg */
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
if (mod != 3) {
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
} else {
gen_op_mov_reg_T0(ot, rm);
}
@@ -5187,7 +5196,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op >= 2 && op != 3 && op != 5)
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -5218,9 +5227,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 3: /* lcall Ev */
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
- gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
+ gen_op_ldu_T0_A0(s, OT_WORD);
do_lcall:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5244,9 +5253,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 5: /* ljmp Ev */
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
- gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
+ gen_op_ldu_T0_A0(s, OT_WORD);
do_ljmp:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5409,9 +5418,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_op_addl_T0_T1();
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
gen_op_mov_reg_T1(ot, reg);
}
gen_op_update2_cc();
@@ -5441,7 +5450,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_mov_tl(a0, cpu_A0);
- gen_op_ld_v(ot + s->mem_index, t0, a0);
+ gen_op_ld_v(s, ot, t0, a0);
rm = 0; /* avoid warning */
}
label1 = gen_new_label();
@@ -5459,11 +5468,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* perform no-op store cycle like physical cpu; must be
before changing accumulator to ensure idempotency if
the store faults and the instruction is restarted */
- gen_op_st_v(ot + s->mem_index, t0, a0);
+ gen_op_st_v(s, ot, t0, a0);
gen_op_mov_reg_v(ot, R_EAX, t0);
tcg_gen_br(label2);
gen_set_label(label1);
- gen_op_st_v(ot + s->mem_index, t1, a0);
+ gen_op_st_v(s, ot, t1, a0);
}
gen_set_label(label2);
tcg_gen_mov_tl(cpu_cc_src, t0);
@@ -5671,7 +5680,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
gen_op_movl_T0_im(val);
if (mod != 3)
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
else
gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
break;
@@ -5757,9 +5766,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (b & 8) {
- gen_op_lds_T0_A0(ot + s->mem_index);
+ gen_op_lds_T0_A0(s, ot);
} else {
- gen_op_ldu_T0_A0(ot + s->mem_index);
+ gen_op_ldu_T0_A0(s, ot);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -5810,11 +5819,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
gen_op_mov_reg_T0(ot, R_EAX);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
}
}
break;
@@ -5838,7 +5847,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
}
gen_add_A0_ds_seg(s);
- gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
+ gen_op_ldu_T0_A0(s, OT_BYTE);
gen_op_mov_reg_T0(OT_BYTE, R_EAX);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
@@ -5895,8 +5904,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
- gen_op_ld_T1_A0(ot + s->mem_index);
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
+ gen_op_st_T0_A0(s, ot);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
gen_op_mov_reg_T1(ot, reg);
@@ -5926,10 +5935,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(ot + s->mem_index);
+ gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
/* load the segment first to handle exceptions properly */
- gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
+ gen_op_ldu_T0_A0(s, OT_WORD);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
gen_op_mov_reg_T1(ot, reg);
@@ -6053,12 +6062,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6069,7 +6078,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(OT_WORD + s->mem_index);
+ gen_op_lds_T0_A0(s, OT_WORD);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6092,12 +6101,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6108,7 +6117,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(OT_WORD + s->mem_index);
+ gen_op_lds_T0_A0(s, OT_WORD);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6120,7 +6129,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 1:
gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
@@ -6131,7 +6140,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
break;
}
gen_helper_fpop(cpu_env);
@@ -6141,12 +6150,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
break;
case 1:
gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
@@ -6157,7 +6166,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
break;
}
if ((op & 7) == 3)
@@ -6171,7 +6180,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
break;
case 0x0d: /* fldcw mem */
- gen_op_ld_T0_A0(OT_WORD + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_WORD);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
break;
@@ -6183,7 +6192,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
break;
case 0x1d: /* fldt mem */
gen_update_cc_op(s);
@@ -6209,7 +6218,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
break;
case 0x3c: /* fbld */
gen_update_cc_op(s);
@@ -6780,7 +6789,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
+ gen_op_ld_T0_A0(s, 1 + s->dflag);
if (s->dflag == 0)
gen_op_andl_T0_ffff();
/* NOTE: keeping EIP updated is not a problem in case of
@@ -6788,7 +6797,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_jmp_T0();
/* pop selector */
gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
+ gen_op_ld_T0_A0(s, 1 + s->dflag);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
gen_stack_update(s, val + (4 << s->dflag));
@@ -7035,7 +7044,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
s->rip_offset = 1;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -7071,7 +7080,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- gen_op_ld_T0_A0(ot + s->mem_index);
+ gen_op_ld_T0_A0(s, ot);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -7106,7 +7115,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_SARB + ot);
if (op != 0) {
if (mod != 3)
- gen_op_st_T0_A0(ot + s->mem_index);
+ gen_op_st_T0_A0(s, ot);
else
gen_op_mov_reg_T0(ot, rm);
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
@@ -7571,12 +7580,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, CODE64(s) + OT_LONG);
break;
case 1:
if (mod == 3) {
@@ -7634,12 +7643,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
- gen_op_st_T0_A0(OT_WORD + s->mem_index);
+ gen_op_st_T0_A0(s, OT_WORD);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, CODE64(s) + OT_LONG);
}
break;
case 2: /* lgdt */
@@ -7734,9 +7743,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(OT_WORD + s->mem_index);
+ gen_op_ld_T1_A0(s, OT_WORD);
gen_add_A0_im(s, 2);
- gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, CODE64(s) + OT_LONG);
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
if (op == 2) {
@@ -7855,9 +7864,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (d_ot == OT_QUAD) {
- gen_op_lds_T0_A0(OT_LONG + s->mem_index);
+ gen_op_lds_T0_A0(s, OT_LONG);
} else {
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -7879,7 +7888,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = modrm & 7;
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
+ gen_op_ld_v(s, ot, t0, cpu_A0);
a0 = tcg_temp_local_new();
tcg_gen_mov_tl(a0, cpu_A0);
} else {
@@ -7897,7 +7906,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_movi_tl(t2, CC_Z);
gen_set_label(label1);
if (mod != 3) {
- gen_op_st_v(ot + s->mem_index, t0, a0);
+ gen_op_st_v(s, ot, t0, a0);
tcg_temp_free(a0);
} else {
gen_op_mov_reg_v(ot, rm, t0);
@@ -8105,12 +8114,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op == 2) {
- gen_op_ld_T0_A0(OT_LONG + s->mem_index);
+ gen_op_ld_T0_A0(s, OT_LONG);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
- gen_op_st_T0_A0(OT_LONG + s->mem_index);
+ gen_op_st_T0_A0(s, OT_LONG);
}
break;
case 5: /* lfence */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 03/60] target-i386: Stop encoding DisasContext.mem_index
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 01/60] exec: Delay CPU_LOG_TB_CPU until we actually execute a TB Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 02/60] target-i386: Push DisasContext into load/store helpers Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 04/60] target-i386: Use new tcg_gen_qemu_ld_* helpers Richard Henderson
` (57 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
Now that we don't combine mem_index with operand size info,
we don't need to encode it. Which tidies many places that
access it.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 67 ++++++++++++++++++-------------------------------
1 file changed, 25 insertions(+), 42 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8c5c16b..40e4826 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,7 +586,7 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
@@ -603,7 +603,7 @@ static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8u(t0, a0, mem_index);
@@ -642,7 +642,7 @@ static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_st8(t0, a0, mem_index);
@@ -2848,21 +2848,19 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
}
static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
}
static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -2872,7 +2870,7 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -3907,15 +3905,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
offsetof(XMMReg, XMM_L(0)));
break;
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
- tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
offsetof(XMMReg, XMM_W(0)));
break;
@@ -4375,8 +4371,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st8(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x15: /* pextrw */
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
@@ -4384,8 +4379,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st16(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x16:
if (ot == OT_LONG) { /* pextrd */
@@ -4396,8 +4390,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
} else { /* pextrq */
#ifdef TARGET_X86_64
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
@@ -4407,7 +4400,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
else
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ s->mem_index);
#else
goto illegal_op;
#endif
@@ -4419,15 +4412,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x20: /* pinsrb */
if (mod == 3)
gen_op_mov_TN_reg(OT_LONG, 0, rm);
else
- tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, s->mem_index);
tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
break;
@@ -4437,8 +4428,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]
.XMM_L((val >> 6) & 3)));
} else {
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
}
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
@@ -4466,8 +4456,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_v_reg(ot, cpu_tmp0, rm);
else
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
@@ -4478,7 +4467,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
else
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ s->mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
@@ -6072,8 +6061,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6111,8 +6099,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6133,8 +6120,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
break;
case 3:
default:
@@ -6159,8 +6145,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
break;
case 3:
default:
@@ -6232,14 +6217,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fpop(cpu_env);
break;
case 0x3d: /* fildll */
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
break;
case 0x3f: /* fistpll */
gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fpop(cpu_env);
break;
default:
@@ -8320,7 +8303,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
/* select memory access functions */
dc->mem_index = 0;
if (flags & HF_SOFTMMU_MASK) {
- dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
+ dc->mem_index = cpu_mmu_index(env);
}
dc->cpuid_features = env->features[FEAT_1_EDX];
dc->cpuid_ext_features = env->features[FEAT_1_ECX];
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 04/60] target-i386: Use new tcg_gen_qemu_ld_* helpers
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (2 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 03/60] target-i386: Stop encoding DisasContext.mem_index Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 05/60] target-i386: Use new tcg_gen_qemu_st_* helpers Richard Henderson
` (56 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
In preference to the older helpers. Loads only in this patch.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 84 ++++++++++++++++++-------------------------------
1 file changed, 31 insertions(+), 53 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 40e4826..a169524 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,42 +586,12 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
{
- int mem_index = s->mem_index;
- switch(idx & 3) {
- case OT_BYTE:
- tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
- break;
- case OT_WORD:
- tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
- break;
- default:
- case OT_LONG:
- tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
- break;
- }
+ tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, s->mem_index, idx | MO_LE | MO_SIGN);
}
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = s->mem_index;
- switch(idx & 3) {
- case OT_BYTE:
- tcg_gen_qemu_ld8u(t0, a0, mem_index);
- break;
- case OT_WORD:
- tcg_gen_qemu_ld16u(t0, a0, mem_index);
- break;
- case OT_LONG:
- tcg_gen_qemu_ld32u(t0, a0, mem_index);
- break;
- default:
- case OT_QUAD:
- /* Should never happen on 32-bit targets. */
-#ifdef TARGET_X86_64
- tcg_gen_qemu_ld64(t0, a0, mem_index);
-#endif
- break;
- }
+ tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
}
/* XXX: always use ldu or lds */
@@ -2848,7 +2818,7 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
}
@@ -2861,10 +2831,10 @@ static inline void gen_stq_env_A0(DisasContext *s, int offset)
static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
int mem_index = s->mem_index;
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
}
@@ -3905,13 +3875,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
offsetof(XMMReg, XMM_L(0)));
break;
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
- tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
+ s->mem_index, MO_LEUW);
tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
offsetof(XMMReg, XMM_W(0)));
break;
@@ -4415,10 +4386,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x20: /* pinsrb */
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_TN_reg(OT_LONG, 0, rm);
- else
- tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_UB);
+ }
tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
break;
@@ -4428,8 +4401,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]
.XMM_L((val >> 6) & 3)));
} else {
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
}
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]
@@ -4453,21 +4426,24 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x22:
if (ot == OT_LONG) { /* pinsrd */
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_v_reg(ot, cpu_tmp0, rm);
- else
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
+ s->mem_index, MO_LEUL);
+ }
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
} else { /* pinsrq */
#ifdef TARGET_X86_64
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
- else
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- s->mem_index);
+ } else {
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
+ }
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
@@ -6061,7 +6037,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6099,7 +6076,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6217,7 +6195,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fpop(cpu_env);
break;
case 0x3d: /* fildll */
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
break;
case 0x3f: /* fistpll */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 05/60] target-i386: Use new tcg_gen_qemu_st_* helpers
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (3 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 04/60] target-i386: Use new tcg_gen_qemu_ld_* helpers Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 06/60] target-i386: Replace OT_* constants with MO_* constants Richard Henderson
` (55 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
In preference to the older helpers. Stores only in this patch.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 75 ++++++++++++++++++++++---------------------------
1 file changed, 34 insertions(+), 41 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index a169524..c69fcdc 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -612,25 +612,7 @@ static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = s->mem_index;
- switch(idx & 3) {
- case OT_BYTE:
- tcg_gen_qemu_st8(t0, a0, mem_index);
- break;
- case OT_WORD:
- tcg_gen_qemu_st16(t0, a0, mem_index);
- break;
- case OT_LONG:
- tcg_gen_qemu_st32(t0, a0, mem_index);
- break;
- default:
- case OT_QUAD:
- /* Should never happen on 32-bit targets. */
-#ifdef TARGET_X86_64
- tcg_gen_qemu_st64(t0, a0, mem_index);
-#endif
- break;
- }
+ tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
}
static inline void gen_op_st_T0_A0(DisasContext *s, int idx)
@@ -2825,7 +2807,7 @@ static inline void gen_ldq_env_A0(DisasContext *s, int offset)
static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
}
static inline void gen_ldo_env_A0(DisasContext *s, int offset)
@@ -2842,10 +2824,10 @@ static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
int mem_index = s->mem_index;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
}
static inline void gen_op_movo(int d_offset, int s_offset)
@@ -4339,18 +4321,22 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x14: /* pextrb */
tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_T0(ot, rm);
- else
- tcg_gen_qemu_st8(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_UB);
+ }
break;
case 0x15: /* pextrw */
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_W(val & 7)));
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_T0(ot, rm);
- else
- tcg_gen_qemu_st16(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_LEUW);
+ }
break;
case 0x16:
if (ot == OT_LONG) { /* pextrd */
@@ -4358,20 +4344,23 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
- else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_LEUL);
+ }
} else { /* pextrq */
#ifdef TARGET_X86_64
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
- else
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- s->mem_index);
+ } else {
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
+ }
#else
goto illegal_op;
#endif
@@ -4380,10 +4369,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x17: /* extractps */
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
- if (mod == 3)
+ if (mod == 3) {
gen_op_mov_reg_T0(ot, rm);
- else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
+ } else {
+ tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ s->mem_index, MO_LEUL);
+ }
break;
case 0x20: /* pinsrb */
if (mod == 3) {
@@ -6098,7 +6089,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
break;
case 3:
default:
@@ -6123,7 +6115,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
+ s->mem_index, MO_LEQ);
break;
case 3:
default:
@@ -6200,7 +6193,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x3f: /* fistpll */
gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
+ tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
gen_helper_fpop(cpu_env);
break;
default:
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 06/60] target-i386: Replace OT_* constants with MO_* constants
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (4 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 05/60] target-i386: Use new tcg_gen_qemu_st_* helpers Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 07/60] target-i386: Remove gen_op_ld_T0_A0 Richard Henderson
` (54 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
The MO_8/16/32/64 constants have the same encoding and meaning
as the OT_BYTE/WORD/LONG/QUAD. Since we rely on them being the
same, for the qemu_ld/st helpers, standardize on the common names.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 710 ++++++++++++++++++++++++------------------------
1 file changed, 351 insertions(+), 359 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c69fcdc..87f4470 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -163,14 +163,6 @@ enum {
JCC_LE,
};
-/* operand size */
-enum {
- OT_BYTE = 0,
- OT_WORD,
- OT_LONG,
- OT_QUAD,
-};
-
enum {
/* I386 int registers */
OR_EAX, /* MUST be even numbered */
@@ -373,24 +365,24 @@ static inline bool byte_reg_is_xH(int reg)
static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
{
switch(ot) {
- case OT_BYTE:
+ case MO_8:
if (!byte_reg_is_xH(reg)) {
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
} else {
tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
}
break;
- case OT_WORD:
+ case MO_16:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
break;
default: /* XXX this shouldn't be reached; abort? */
- case OT_LONG:
+ case MO_32:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], t0);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_mov_tl(cpu_regs[reg], t0);
break;
#endif
@@ -410,17 +402,17 @@ static inline void gen_op_mov_reg_T1(int ot, int reg)
static inline void gen_op_mov_reg_A0(int size, int reg)
{
switch(size) {
- case OT_BYTE:
+ case MO_8:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
break;
default: /* XXX this shouldn't be reached; abort? */
- case OT_WORD:
+ case MO_16:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
break;
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
break;
#endif
@@ -429,7 +421,7 @@ static inline void gen_op_mov_reg_A0(int size, int reg)
static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
{
- if (ot == OT_BYTE && byte_reg_is_xH(reg)) {
+ if (ot == MO_8 && byte_reg_is_xH(reg)) {
tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
tcg_gen_ext8u_tl(t0, t0);
} else {
@@ -485,11 +477,11 @@ static inline void gen_op_jmp_T0(void)
static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
{
switch(size) {
- case OT_BYTE:
+ case MO_8:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
break;
- case OT_WORD:
+ case MO_16:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
@@ -497,7 +489,7 @@ static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
break;
#endif
@@ -507,11 +499,11 @@ static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
static inline void gen_op_add_reg_T0(int size, int reg)
{
switch(size) {
- case OT_BYTE:
+ case MO_8:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
break;
- case OT_WORD:
+ case MO_16:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
@@ -519,7 +511,7 @@ static inline void gen_op_add_reg_T0(int size, int reg)
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
break;
#endif
@@ -696,14 +688,14 @@ static inline void gen_op_movl_T0_Dshift(int ot)
static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
{
switch (size) {
- case OT_BYTE:
+ case MO_8:
if (sign) {
tcg_gen_ext8s_tl(dst, src);
} else {
tcg_gen_ext8u_tl(dst, src);
}
return dst;
- case OT_WORD:
+ case MO_16:
if (sign) {
tcg_gen_ext16s_tl(dst, src);
} else {
@@ -711,7 +703,7 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
}
return dst;
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
if (sign) {
tcg_gen_ext32s_tl(dst, src);
} else {
@@ -751,13 +743,13 @@ static inline void gen_op_jz_ecx(int size, int label1)
static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_inb(v, n);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_inw(v, n);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_inl(v, n);
break;
}
@@ -766,13 +758,13 @@ static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
{
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_outb(v, n);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_outw(v, n);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_outl(v, n);
break;
}
@@ -791,13 +783,13 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
state_saved = 1;
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_check_iow(cpu_env, cpu_tmp2_i32);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
break;
}
@@ -1244,7 +1236,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
static inline void gen_stos(DisasContext *s, int ot)
{
- gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_32, 0, R_EAX);
gen_string_movl_A0_EDI(s);
gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
@@ -1289,7 +1281,7 @@ static inline void gen_ins(DisasContext *s, int ot)
case of page fault. */
gen_op_movl_T0_0();
gen_op_st_T0_A0(s, ot);
- gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
+ gen_op_mov_TN_reg(MO_16, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
@@ -1307,7 +1299,7 @@ static inline void gen_outs(DisasContext *s, int ot)
gen_string_movl_A0_ESI(s);
gen_op_ld_T0_A0(s, ot);
- gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
+ gen_op_mov_TN_reg(MO_16, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
@@ -1576,7 +1568,7 @@ static void gen_shift_flags(DisasContext *s, int ot, TCGv result, TCGv shm1,
static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
int is_right, int is_arith)
{
- target_ulong mask = (ot == OT_QUAD ? 0x3f : 0x1f);
+ target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
/* load */
if (op1 == OR_TMP0) {
@@ -1616,7 +1608,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
int is_right, int is_arith)
{
- int mask = (ot == OT_QUAD ? 0x3f : 0x1f);
+ int mask = (ot == MO_64 ? 0x3f : 0x1f);
/* load */
if (op1 == OR_TMP0)
@@ -1666,7 +1658,7 @@ static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
{
- target_ulong mask = (ot == OT_QUAD ? 0x3f : 0x1f);
+ target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
TCGv_i32 t0, t1;
/* load */
@@ -1679,18 +1671,18 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
switch (ot) {
- case OT_BYTE:
+ case MO_8:
/* Replicate the 8-bit input so that a 32-bit rotate works. */
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_muli_tl(cpu_T[0], cpu_T[0], 0x01010101);
goto do_long;
- case OT_WORD:
+ case MO_16:
/* Replicate the 16-bit input so that a 32-bit rotate works. */
tcg_gen_deposit_tl(cpu_T[0], cpu_T[0], cpu_T[0], 16, 16);
goto do_long;
do_long:
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
if (is_right) {
@@ -1756,7 +1748,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
int is_right)
{
- int mask = (ot == OT_QUAD ? 0x3f : 0x1f);
+ int mask = (ot == MO_64 ? 0x3f : 0x1f);
int shift;
/* load */
@@ -1770,7 +1762,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
if (op2 != 0) {
switch (ot) {
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
if (is_right) {
tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2);
@@ -1787,10 +1779,10 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
tcg_gen_rotli_tl(cpu_T[0], cpu_T[0], op2);
}
break;
- case OT_BYTE:
+ case MO_8:
mask = 7;
goto do_shifts;
- case OT_WORD:
+ case MO_16:
mask = 15;
do_shifts:
shift = op2 & mask;
@@ -1849,34 +1841,34 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
if (is_right) {
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
}
} else {
switch (ot) {
- case OT_BYTE:
+ case MO_8:
gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case OT_WORD:
+ case MO_16:
gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
- case OT_LONG:
+ case MO_32:
gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
@@ -1893,7 +1885,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
bool is_right, TCGv count_in)
{
- target_ulong mask = (ot == OT_QUAD ? 63 : 31);
+ target_ulong mask = (ot == MO_64 ? 63 : 31);
TCGv count;
/* load */
@@ -1907,7 +1899,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
tcg_gen_andi_tl(count, count_in, mask);
switch (ot) {
- case OT_WORD:
+ case MO_16:
/* Note: we implement the Intel behaviour for shift count > 16.
This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
portion by constructing it as a 32-bit value. */
@@ -1920,7 +1912,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
}
/* FALLTHRU */
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
/* Concatenate the two 32-bit values and use a 64-bit shift. */
tcg_gen_subi_tl(cpu_tmp0, count, 1);
if (is_right) {
@@ -1946,7 +1938,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp4);
} else {
tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
- if (ot == OT_WORD) {
+ if (ot == MO_16) {
/* Only needed if count > 16, for Intel behaviour. */
tcg_gen_subfi_tl(cpu_tmp4, 33, count);
tcg_gen_shr_tl(cpu_tmp4, cpu_T[1], cpu_tmp4);
@@ -2329,16 +2321,16 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
uint32_t ret;
switch(ot) {
- case OT_BYTE:
+ case MO_8:
ret = cpu_ldub_code(env, s->pc);
s->pc++;
break;
- case OT_WORD:
+ case MO_16:
ret = cpu_lduw_code(env, s->pc);
s->pc += 2;
break;
default:
- case OT_LONG:
+ case MO_32:
ret = cpu_ldl_code(env, s->pc);
s->pc += 4;
break;
@@ -2348,7 +2340,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
static inline int insn_const_size(unsigned int ot)
{
- if (ot <= OT_LONG)
+ if (ot <= MO_32)
return 1 << ot;
else
return 4;
@@ -2518,10 +2510,10 @@ static void gen_push_T0(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T0_A0(s, OT_QUAD);
+ gen_op_st_T0_A0(s, MO_64);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2559,10 +2551,10 @@ static void gen_push_T1(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T1_A0(s, OT_QUAD);
+ gen_op_st_T1_A0(s, MO_64);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2596,7 +2588,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_T0_A0(s, s->dflag ? OT_QUAD : OT_WORD);
+ gen_op_ld_T0_A0(s, s->dflag ? MO_64 : MO_16);
} else
#endif
{
@@ -2646,11 +2638,11 @@ static void gen_pusha(DisasContext *s)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
- gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
- gen_op_st_T0_A0(s, OT_WORD + s->dflag);
+ gen_op_mov_TN_reg(MO_32, 0, 7 - i);
+ gen_op_st_T0_A0(s, MO_16 + s->dflag);
gen_op_addl_A0_im(2 << s->dflag);
}
- gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
+ gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
/* NOTE: wrap around in 16 bit not fully handled */
@@ -2667,12 +2659,12 @@ static void gen_popa(DisasContext *s)
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_T0_A0(s, OT_WORD + s->dflag);
- gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
+ gen_op_ld_T0_A0(s, MO_16 + s->dflag);
+ gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i);
}
gen_op_addl_A0_im(2 << s->dflag);
}
- gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
+ gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
@@ -2682,7 +2674,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
level &= 0x1f;
#ifdef TARGET_X86_64
if (CODE64(s)) {
- ot = s->dflag ? OT_QUAD : OT_WORD;
+ ot = s->dflag ? MO_64 : MO_16;
opsize = 1 << ot;
gen_op_movl_A0_reg(R_ESP);
@@ -2690,21 +2682,21 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
/* push bp */
- gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
+ gen_op_mov_TN_reg(MO_32, 0, R_EBP);
gen_op_st_T0_A0(s, ot);
if (level) {
/* XXX: must save state */
gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
- tcg_const_i32((ot == OT_QUAD)),
+ tcg_const_i32((ot == MO_64)),
cpu_T[1]);
}
gen_op_mov_reg_T1(ot, R_EBP);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(OT_QUAD, R_ESP);
+ gen_op_mov_reg_T1(MO_64, R_ESP);
} else
#endif
{
- ot = s->dflag + OT_WORD;
+ ot = s->dflag + MO_16;
opsize = 2 << s->dflag;
gen_op_movl_A0_reg(R_ESP);
@@ -2715,7 +2707,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
/* push bp */
- gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
+ gen_op_mov_TN_reg(MO_32, 0, R_EBP);
gen_op_st_T0_A0(s, ot);
if (level) {
/* XXX: must save state */
@@ -2725,7 +2717,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
}
gen_op_mov_reg_T1(ot, R_EBP);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
+ gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
}
@@ -3288,18 +3280,18 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
}
break;
case 0x6e: /* movd mm, ea */
#ifdef TARGET_X86_64
if (s->dflag == 2) {
- gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
} else
#endif
{
- gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -3309,14 +3301,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x16e: /* movd xmm, ea */
#ifdef TARGET_X86_64
if (s->dflag == 2) {
- gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
} else
#endif
{
- gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -3353,7 +3345,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x210: /* movss xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_movl_T0_0();
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
@@ -3476,13 +3468,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (s->dflag == 2) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
- gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
} else
#endif
{
tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
- gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
}
break;
case 0x17e: /* movd ea, xmm */
@@ -3490,13 +3482,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (s->dflag == 2) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
- gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
} else
#endif
{
tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
}
break;
case 0x27e: /* movq xmm, ea */
@@ -3540,7 +3532,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
@@ -3623,7 +3615,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(OT_LONG, reg);
+ gen_op_mov_reg_T0(MO_32, reg);
break;
case 0x150: /* movmskpd */
rm = (modrm & 7) | REX_B(s);
@@ -3631,7 +3623,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(OT_LONG, reg);
+ gen_op_mov_reg_T0(MO_32, reg);
break;
case 0x02a: /* cvtpi2ps */
case 0x12a: /* cvtpi2pd */
@@ -3659,11 +3651,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x22a: /* cvtsi2ss */
case 0x32a: /* cvtsi2sd */
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
- if (ot == OT_LONG) {
+ if (ot == MO_32) {
SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32);
@@ -3711,13 +3703,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x32c: /* cvttsd2si */
case 0x22d: /* cvtss2si */
case 0x32d: /* cvtsd2si */
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if ((b >> 8) & 1) {
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
}
op2_offset = offsetof(CPUX86State,xmm_t0);
@@ -3726,7 +3718,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
}
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
- if (ot == OT_LONG) {
+ if (ot == MO_32) {
SSEFunc_i_ep sse_fn_i_ep =
sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
@@ -3745,7 +3737,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0xc4: /* pinsrw */
case 0x1c4:
s->rip_offset = 1;
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
@@ -3761,7 +3753,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x1c5:
if (mod != 3)
goto illegal_op;
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
@@ -3817,7 +3809,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_T0(OT_LONG, reg);
+ gen_op_mov_reg_T0(MO_32, reg);
break;
case 0x138:
@@ -3914,20 +3906,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
}
if ((b & 0xff) == 0xf0) {
- ot = OT_BYTE;
+ ot = MO_8;
} else if (s->dflag != 2) {
- ot = (s->prefix & PREFIX_DATA ? OT_WORD : OT_LONG);
+ ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
- ot = OT_QUAD;
+ ot = MO_64;
}
- gen_op_mov_TN_reg(OT_LONG, 0, reg);
+ gen_op_mov_TN_reg(MO_32, 0, reg);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
cpu_T[0], tcg_const_i32(8 << ot));
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
gen_op_mov_reg_T0(ot, reg);
break;
@@ -3946,9 +3938,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
}
if (s->dflag != 2) {
- ot = (s->prefix & PREFIX_DATA ? OT_WORD : OT_LONG);
+ ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
- ot = OT_QUAD;
+ ot = MO_64;
}
/* Load the data incoming to the bswap. Note that the TCG
@@ -3959,27 +3951,27 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
} else {
switch (ot) {
- case OT_WORD:
+ case MO_16:
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[reg]);
break;
default:
tcg_gen_ext32u_tl(cpu_T[0], cpu_regs[reg]);
break;
- case OT_QUAD:
+ case MO_64:
tcg_gen_mov_tl(cpu_T[0], cpu_regs[reg]);
break;
}
}
switch (ot) {
- case OT_WORD:
+ case MO_16:
tcg_gen_bswap16_tl(cpu_T[0], cpu_T[0]);
break;
default:
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_bswap64_tl(cpu_T[0], cpu_T[0]);
break;
#endif
@@ -3998,7 +3990,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
gen_op_mov_reg_T0(ot, reg);
@@ -4012,7 +4004,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
{
TCGv bound, zero;
@@ -4022,7 +4014,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ext8u_tl(cpu_A0, cpu_regs[s->vex_v]);
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_A0);
- bound = tcg_const_tl(ot == OT_QUAD ? 63 : 31);
+ bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
zero = tcg_const_tl(0);
tcg_gen_movcond_tl(TCG_COND_LEU, cpu_T[0], cpu_A0, bound,
cpu_T[0], zero);
@@ -4052,11 +4044,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]);
{
- TCGv bound = tcg_const_tl(ot == OT_QUAD ? 63 : 31);
+ TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
/* Note that since we're using BMILG (in order to get O
cleared) we need to store the inverse into C. */
tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src,
@@ -4079,7 +4071,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (ot) {
default:
@@ -4091,7 +4083,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp3_i32);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],
cpu_T[0], cpu_regs[R_EDX]);
break;
@@ -4105,7 +4097,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
@@ -4123,7 +4115,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
@@ -4143,7 +4135,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
TCGv carry_in, carry_out, zero;
int end_op;
- ot = (s->dflag == 2 ? OT_QUAD : OT_LONG);
+ ot = (s->dflag == 2 ? MO_64 : MO_32);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Re-use the carry-out from a previous round. */
@@ -4187,7 +4179,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
switch (ot) {
#ifdef TARGET_X86_64
- case OT_LONG:
+ case MO_32:
/* If we know TL is 64-bit, and we want a 32-bit
result, just do everything in 64-bit arithmetic. */
tcg_gen_ext32u_i64(cpu_regs[reg], cpu_regs[reg]);
@@ -4222,9 +4214,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = (s->dflag == 2 ? OT_QUAD : OT_LONG);
+ ot = (s->dflag == 2 ? MO_64 : MO_32);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- if (ot == OT_QUAD) {
+ if (ot == MO_64) {
tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
} else {
tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 31);
@@ -4232,12 +4224,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (b == 0x1f7) {
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
} else if (b == 0x2f7) {
- if (ot != OT_QUAD) {
+ if (ot != MO_64) {
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
}
tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
} else {
- if (ot != OT_QUAD) {
+ if (ot != MO_64) {
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
}
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
@@ -4254,7 +4246,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (reg & 7) {
@@ -4311,7 +4303,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
if (sse_fn_eppi == SSE_SPECIAL) {
- ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
+ ot = (s->dflag == 2) ? MO_64 : MO_32;
rm = (modrm & 7) | REX_B(s);
if (mod != 3)
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
@@ -4339,7 +4331,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
break;
case 0x16:
- if (ot == OT_LONG) { /* pextrd */
+ if (ot == MO_32) { /* pextrd */
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
@@ -4378,7 +4370,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x20: /* pinsrb */
if (mod == 3) {
- gen_op_mov_TN_reg(OT_LONG, 0, rm);
+ gen_op_mov_TN_reg(MO_32, 0, rm);
} else {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
@@ -4416,7 +4408,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
xmm_regs[reg].XMM_L(3)));
break;
case 0x22:
- if (ot == OT_LONG) { /* pinsrd */
+ if (ot == MO_32) { /* pinsrd */
if (mod == 3) {
gen_op_mov_v_reg(ot, cpu_tmp0, rm);
} else {
@@ -4494,10 +4486,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
b = cpu_ldub_code(env, s->pc++);
- if (ot == OT_QUAD) {
+ if (ot == MO_64) {
tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], b & 63);
} else {
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -4536,7 +4528,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* specific case for SSE single instructions */
if (b1 == 2) {
/* 32 bit access */
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
} else {
/* 64 bit access */
@@ -4819,9 +4811,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
f = (b >> 1) & 3;
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
switch(f) {
case 0: /* OP Ev, Gv */
@@ -4879,9 +4871,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
int val;
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4907,7 +4899,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
break;
case 0x83:
- val = (int8_t)insn_get(env, s, OT_BYTE);
+ val = (int8_t)insn_get(env, s, MO_8);
break;
}
gen_op_movl_T1_im(val);
@@ -4918,19 +4910,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* inc, dec, and other misc arith */
case 0x40 ... 0x47: /* inc Gv */
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
gen_inc(s, ot, OR_EAX + (b & 7), 1);
break;
case 0x48 ... 0x4f: /* dec Gv */
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
gen_inc(s, ot, OR_EAX + (b & 7), -1);
break;
case 0xf6: /* GRP3 */
case 0xf7:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4972,32 +4964,32 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 4: /* mul */
switch(ot) {
- case OT_BYTE:
- gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
+ case MO_8:
+ gen_op_mov_TN_reg(MO_8, 1, R_EAX);
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
set_cc_op(s, CC_OP_MULB);
break;
- case OT_WORD:
- gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
+ case MO_16:
+ gen_op_mov_TN_reg(MO_16, 1, R_EAX);
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(OT_WORD, R_EDX);
+ gen_op_mov_reg_T0(MO_16, R_EDX);
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
default:
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
@@ -5009,7 +5001,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
cpu_T[0], cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
@@ -5021,34 +5013,34 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 5: /* imul */
switch(ot) {
- case OT_BYTE:
- gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
+ case MO_8:
+ gen_op_mov_TN_reg(MO_8, 1, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
set_cc_op(s, CC_OP_MULB);
break;
- case OT_WORD:
- gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
+ case MO_16:
+ gen_op_mov_TN_reg(MO_16, 1, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(OT_WORD, R_EDX);
+ gen_op_mov_reg_T0(MO_16, R_EDX);
set_cc_op(s, CC_OP_MULW);
break;
default:
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
@@ -5062,7 +5054,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
cpu_T[0], cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
@@ -5075,21 +5067,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 6: /* div */
switch(ot) {
- case OT_BYTE:
+ case MO_8:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_divb_AL(cpu_env, cpu_T[0]);
break;
- case OT_WORD:
+ case MO_16:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_divw_AX(cpu_env, cpu_T[0]);
break;
default:
- case OT_LONG:
+ case MO_32:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_divl_EAX(cpu_env, cpu_T[0]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_divq_EAX(cpu_env, cpu_T[0]);
break;
@@ -5098,21 +5090,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 7: /* idiv */
switch(ot) {
- case OT_BYTE:
+ case MO_8:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_idivb_AL(cpu_env, cpu_T[0]);
break;
- case OT_WORD:
+ case MO_16:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_idivw_AX(cpu_env, cpu_T[0]);
break;
default:
- case OT_LONG:
+ case MO_32:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_idivl_EAX(cpu_env, cpu_T[0]);
break;
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
gen_jmp_im(pc_start - s->cs_base);
gen_helper_idivq_EAX(cpu_env, cpu_T[0]);
break;
@@ -5127,9 +5119,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xfe: /* GRP4 */
case 0xff: /* GRP5 */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -5141,12 +5133,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s)) {
if (op == 2 || op == 4) {
/* operand size for jumps is 64 bit */
- ot = OT_QUAD;
+ ot = MO_64;
} else if (op == 3 || op == 5) {
- ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
+ ot = dflag ? MO_32 + (rex_w == 1) : MO_16;
} else if (op == 6) {
/* default push size is 64 bit */
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
}
}
if (mod != 3) {
@@ -5184,8 +5176,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3: /* lcall Ev */
gen_op_ld_T1_A0(s, ot);
- gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
- gen_op_ldu_T0_A0(s, OT_WORD);
+ gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_op_ldu_T0_A0(s, MO_16);
do_lcall:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5210,8 +5202,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 5: /* ljmp Ev */
gen_op_ld_T1_A0(s, ot);
- gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
- gen_op_ldu_T0_A0(s, OT_WORD);
+ gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_op_ldu_T0_A0(s, MO_16);
do_ljmp:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5237,9 +5229,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x84: /* test Ev, Gv */
case 0x85:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5253,9 +5245,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa8: /* test eAX, Iv */
case 0xa9:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
val = insn_get(env, s, ot);
gen_op_mov_TN_reg(ot, 0, OR_EAX);
@@ -5267,45 +5259,45 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x98: /* CWDE/CBW */
#ifdef TARGET_X86_64
if (dflag == 2) {
- gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_QUAD, R_EAX);
+ gen_op_mov_reg_T0(MO_64, R_EAX);
} else
#endif
if (dflag == 1) {
- gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_LONG, R_EAX);
+ gen_op_mov_reg_T0(MO_32, R_EAX);
} else {
- gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_8, 0, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
}
break;
case 0x99: /* CDQ/CWD */
#ifdef TARGET_X86_64
if (dflag == 2) {
- gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
- gen_op_mov_reg_T0(OT_QUAD, R_EDX);
+ gen_op_mov_reg_T0(MO_64, R_EDX);
} else
#endif
if (dflag == 1) {
- gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
- gen_op_mov_reg_T0(OT_LONG, R_EDX);
+ gen_op_mov_reg_T0(MO_32, R_EDX);
} else {
- gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
- gen_op_mov_reg_T0(OT_WORD, R_EDX);
+ gen_op_mov_reg_T0(MO_16, R_EDX);
}
break;
case 0x1af: /* imul Gv, Ev */
case 0x69: /* imul Gv, Ev, I */
case 0x6b:
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
if (b == 0x69)
@@ -5317,21 +5309,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
gen_op_movl_T1_im(val);
} else if (b == 0x6b) {
- val = (int8_t)insn_get(env, s, OT_BYTE);
+ val = (int8_t)insn_get(env, s, MO_8);
gen_op_movl_T1_im(val);
} else {
gen_op_mov_TN_reg(ot, 1, reg);
}
switch (ot) {
#ifdef TARGET_X86_64
- case OT_QUAD:
+ case MO_64:
tcg_gen_muls2_i64(cpu_regs[reg], cpu_T[1], cpu_T[0], cpu_T[1]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);
tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_T[1]);
break;
#endif
- case OT_LONG:
+ case MO_32:
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
@@ -5358,9 +5350,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c0:
case 0x1c1: /* xadd Ev, Gv */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5389,9 +5381,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGv t0, t1, t2, a0;
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5470,14 +5462,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
- gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
+ gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s));
gen_push_T0(s);
break;
case 0x58 ... 0x5f: /* pop */
if (CODE64(s)) {
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
} else {
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
}
gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
@@ -5497,22 +5489,22 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x68: /* push Iv */
case 0x6a:
if (CODE64(s)) {
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
} else {
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
}
if (b == 0x68)
val = insn_get(env, s, ot);
else
- val = (int8_t)insn_get(env, s, OT_BYTE);
+ val = (int8_t)insn_get(env, s, MO_8);
gen_op_movl_T0_im(val);
gen_push_T0(s);
break;
case 0x8f: /* pop Ev */
if (CODE64(s)) {
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
} else {
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
}
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -5542,20 +5534,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc9: /* leave */
/* XXX: exception not precise (ESP is updated before potential exception) */
if (CODE64(s)) {
- gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
- gen_op_mov_reg_T0(OT_QUAD, R_ESP);
+ gen_op_mov_TN_reg(MO_64, 0, R_EBP);
+ gen_op_mov_reg_T0(MO_64, R_ESP);
} else if (s->ss32) {
- gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
- gen_op_mov_reg_T0(OT_LONG, R_ESP);
+ gen_op_mov_TN_reg(MO_32, 0, R_EBP);
+ gen_op_mov_reg_T0(MO_32, R_ESP);
} else {
- gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
- gen_op_mov_reg_T0(OT_WORD, R_ESP);
+ gen_op_mov_TN_reg(MO_16, 0, R_EBP);
+ gen_op_mov_reg_T0(MO_16, R_ESP);
}
gen_pop_T0(s);
if (CODE64(s)) {
- ot = dflag ? OT_QUAD : OT_WORD;
+ ot = dflag ? MO_64 : MO_16;
} else {
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
}
gen_op_mov_reg_T0(ot, R_EBP);
gen_pop_update(s);
@@ -5612,9 +5604,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x88:
case 0x89: /* mov Gv, Ev */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5624,9 +5616,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc6:
case 0xc7: /* mov Ev, Iv */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod != 3) {
@@ -5643,9 +5635,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x8a:
case 0x8b: /* mov Ev, Gv */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = OT_WORD + dflag;
+ ot = MO_16 + dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5657,7 +5649,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = (modrm >> 3) & 7;
if (reg >= 6 || reg == R_CS)
goto illegal_op;
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
if (reg == R_SS) {
/* if reg == SS, inhibit interrupts/trace */
@@ -5680,9 +5672,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_op_movl_T0_seg(reg);
if (mod == 3)
- ot = OT_WORD + dflag;
+ ot = MO_16 + dflag;
else
- ot = OT_WORD;
+ ot = MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
@@ -5693,9 +5685,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int d_ot;
/* d_ot is the size of destination */
- d_ot = dflag + OT_WORD;
+ d_ot = dflag + MO_16;
/* ot is the size of source */
- ot = (b & 1) + OT_BYTE;
+ ot = (b & 1) + MO_8;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5704,17 +5696,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3) {
gen_op_mov_TN_reg(ot, 0, rm);
switch(ot | (b & 8)) {
- case OT_BYTE:
+ case MO_8:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
break;
- case OT_BYTE | 8:
+ case MO_8 | 8:
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
break;
- case OT_WORD:
+ case MO_16:
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
break;
default:
- case OT_WORD | 8:
+ case MO_16 | 8:
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
@@ -5732,7 +5724,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x8d: /* lea */
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -5744,7 +5736,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->addseg = 0;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
s->addseg = val;
- gen_op_mov_reg_A0(ot - OT_WORD, reg);
+ gen_op_mov_reg_A0(ot - MO_16, reg);
break;
case 0xa0: /* mov EAX, Ov */
@@ -5755,9 +5747,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong offset_addr;
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
#ifdef TARGET_X86_64
if (s->aflag == 2) {
offset_addr = cpu_ldq_code(env, s->pc);
@@ -5767,9 +5759,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
#endif
{
if (s->aflag) {
- offset_addr = insn_get(env, s, OT_LONG);
+ offset_addr = insn_get(env, s, MO_32);
} else {
- offset_addr = insn_get(env, s, OT_WORD);
+ offset_addr = insn_get(env, s, MO_16);
}
gen_op_movl_A0_im(offset_addr);
}
@@ -5787,14 +5779,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
#ifdef TARGET_X86_64
if (s->aflag == 2) {
gen_op_movq_A0_reg(R_EBX);
- gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
} else
#endif
{
gen_op_movl_A0_reg(R_EBX);
- gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
+ gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
if (s->aflag == 0)
@@ -5803,13 +5795,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
}
gen_add_A0_ds_seg(s);
- gen_op_ldu_T0_A0(s, OT_BYTE);
- gen_op_mov_reg_T0(OT_BYTE, R_EAX);
+ gen_op_ldu_T0_A0(s, MO_8);
+ gen_op_mov_reg_T0(MO_8, R_EAX);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
- val = insn_get(env, s, OT_BYTE);
+ val = insn_get(env, s, MO_8);
gen_op_movl_T0_im(val);
- gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
+ gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
@@ -5820,11 +5812,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->pc += 8;
reg = (b & 7) | REX_B(s);
gen_movtl_T0_im(tmp);
- gen_op_mov_reg_T0(OT_QUAD, reg);
+ gen_op_mov_reg_T0(MO_64, reg);
} else
#endif
{
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
gen_op_movl_T0_im(val);
@@ -5834,16 +5826,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x91 ... 0x97: /* xchg R, EAX */
do_xchg_reg_eax:
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
reg = (b & 7) | REX_B(s);
rm = R_EAX;
goto do_xchg_reg;
case 0x86:
case 0x87: /* xchg Ev, Gv */
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5884,7 +5876,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1b5: /* lgs Gv */
op = R_GS;
do_lxx:
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5892,9 +5884,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_op_ld_T1_A0(s, ot);
- gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
+ gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
/* load the segment first to handle exceptions properly */
- gen_op_ldu_T0_A0(s, OT_WORD);
+ gen_op_ldu_T0_A0(s, MO_16);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
gen_op_mov_reg_T1(ot, reg);
@@ -5913,9 +5905,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
grp2:
{
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -5969,7 +5961,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = 1;
shift = 0;
do_shiftd:
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
@@ -6018,12 +6010,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6034,7 +6026,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(s, OT_WORD);
+ gen_op_lds_T0_A0(s, MO_16);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6057,12 +6049,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6073,7 +6065,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(s, OT_WORD);
+ gen_op_lds_T0_A0(s, MO_16);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6085,7 +6077,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 1:
gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
@@ -6096,7 +6088,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
break;
}
gen_helper_fpop(cpu_env);
@@ -6106,12 +6098,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
break;
case 1:
gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
@@ -6122,7 +6114,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
break;
}
if ((op & 7) == 3)
@@ -6136,7 +6128,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
break;
case 0x0d: /* fldcw mem */
- gen_op_ld_T0_A0(s, OT_WORD);
+ gen_op_ld_T0_A0(s, MO_16);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
break;
@@ -6148,7 +6140,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
break;
case 0x1d: /* fldt mem */
gen_update_cc_op(s);
@@ -6174,7 +6166,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
break;
case 0x3c: /* fbld */
gen_update_cc_op(s);
@@ -6459,7 +6451,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(OT_WORD, R_EAX);
+ gen_op_mov_reg_T0(MO_16, R_EAX);
break;
default:
goto illegal_op;
@@ -6517,9 +6509,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa4: /* movsS */
case 0xa5:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
@@ -6531,9 +6523,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xaa: /* stosS */
case 0xab:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
@@ -6544,9 +6536,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xac: /* lodsS */
case 0xad:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6556,9 +6548,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xae: /* scasS */
case 0xaf:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & PREFIX_REPNZ) {
gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6571,9 +6563,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa6: /* cmpsS */
case 0xa7:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
if (prefixes & PREFIX_REPNZ) {
gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6585,10 +6577,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x6c: /* insS */
case 0x6d:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
+ ot = dflag ? MO_32 : MO_16;
+ gen_op_mov_TN_reg(MO_16, 0, R_EDX);
gen_op_andl_T0_ffff();
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
@@ -6604,10 +6596,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x6e: /* outsS */
case 0x6f:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
+ ot = dflag ? MO_32 : MO_16;
+ gen_op_mov_TN_reg(MO_16, 0, R_EDX);
gen_op_andl_T0_ffff();
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
@@ -6627,9 +6619,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe4:
case 0xe5:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
val = cpu_ldub_code(env, s->pc++);
gen_op_movl_T0_im(val);
gen_check_io(s, ot, pc_start - s->cs_base,
@@ -6647,9 +6639,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe6:
case 0xe7:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
val = cpu_ldub_code(env, s->pc++);
gen_op_movl_T0_im(val);
gen_check_io(s, ot, pc_start - s->cs_base,
@@ -6669,10 +6661,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xec:
case 0xed:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
+ ot = dflag ? MO_32 : MO_16;
+ gen_op_mov_TN_reg(MO_16, 0, R_EDX);
gen_op_andl_T0_ffff();
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6689,10 +6681,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xee:
case 0xef:
if ((b & 1) == 0)
- ot = OT_BYTE;
+ ot = MO_8;
else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
+ ot = dflag ? MO_32 : MO_16;
+ gen_op_mov_TN_reg(MO_16, 0, R_EDX);
gen_op_andl_T0_ffff();
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
@@ -6786,9 +6778,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe8: /* call im */
{
if (dflag)
- tval = (int32_t)insn_get(env, s, OT_LONG);
+ tval = (int32_t)insn_get(env, s, MO_32);
else
- tval = (int16_t)insn_get(env, s, OT_WORD);
+ tval = (int16_t)insn_get(env, s, MO_16);
next_eip = s->pc - s->cs_base;
tval += next_eip;
if (s->dflag == 0)
@@ -6806,9 +6798,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
offset = insn_get(env, s, ot);
- selector = insn_get(env, s, OT_WORD);
+ selector = insn_get(env, s, MO_16);
gen_op_movl_T0_im(selector);
gen_op_movl_T1_imu(offset);
@@ -6816,9 +6808,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto do_lcall;
case 0xe9: /* jmp im */
if (dflag)
- tval = (int32_t)insn_get(env, s, OT_LONG);
+ tval = (int32_t)insn_get(env, s, MO_32);
else
- tval = (int16_t)insn_get(env, s, OT_WORD);
+ tval = (int16_t)insn_get(env, s, MO_16);
tval += s->pc - s->cs_base;
if (s->dflag == 0)
tval &= 0xffff;
@@ -6832,29 +6824,29 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
offset = insn_get(env, s, ot);
- selector = insn_get(env, s, OT_WORD);
+ selector = insn_get(env, s, MO_16);
gen_op_movl_T0_im(selector);
gen_op_movl_T1_imu(offset);
}
goto do_ljmp;
case 0xeb: /* jmp Jb */
- tval = (int8_t)insn_get(env, s, OT_BYTE);
+ tval = (int8_t)insn_get(env, s, MO_8);
tval += s->pc - s->cs_base;
if (s->dflag == 0)
tval &= 0xffff;
gen_jmp(s, tval);
break;
case 0x70 ... 0x7f: /* jcc Jb */
- tval = (int8_t)insn_get(env, s, OT_BYTE);
+ tval = (int8_t)insn_get(env, s, MO_8);
goto do_jcc;
case 0x180 ... 0x18f: /* jcc Jv */
if (dflag) {
- tval = (int32_t)insn_get(env, s, OT_LONG);
+ tval = (int32_t)insn_get(env, s, MO_32);
} else {
- tval = (int16_t)insn_get(env, s, OT_WORD);
+ tval = (int16_t)insn_get(env, s, MO_16);
}
do_jcc:
next_eip = s->pc - s->cs_base;
@@ -6867,13 +6859,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x190 ... 0x19f: /* setcc Gv */
modrm = cpu_ldub_code(env, s->pc++);
gen_setcc1(s, b, cpu_T[0]);
- gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1);
break;
case 0x140 ... 0x14f: /* cmov Gv, Ev */
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_cmovcc1(env, s, ot, b, modrm, reg);
@@ -6952,7 +6944,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
- gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
+ gen_op_mov_TN_reg(MO_8, 0, R_AH);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
@@ -6964,7 +6956,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
- gen_op_mov_reg_T0(OT_BYTE, R_AH);
+ gen_op_mov_reg_T0(MO_8, R_AH);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
@@ -6990,7 +6982,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/************************/
/* bit operations */
case 0x1ba: /* bt/bts/btr/btc Gv, im */
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
op = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7021,12 +7013,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1bb: /* btc */
op = 3;
do_btx:
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(OT_LONG, 1, reg);
+ gen_op_mov_TN_reg(MO_32, 1, reg);
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
/* specific case: we need to add a displacement */
@@ -7078,7 +7070,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1bc: /* bsf / tzcnt */
case 0x1bd: /* bsr / lzcnt */
- ot = dflag + OT_WORD;
+ ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
@@ -7277,7 +7269,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x62: /* bound */
if (CODE64(s))
goto illegal_op;
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7287,7 +7279,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- if (ot == OT_WORD) {
+ if (ot == MO_16) {
gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32);
} else {
gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32);
@@ -7297,16 +7289,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == 2) {
- gen_op_mov_TN_reg(OT_QUAD, 0, reg);
+ gen_op_mov_TN_reg(MO_64, 0, reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_QUAD, reg);
+ gen_op_mov_reg_T0(MO_64, reg);
} else
#endif
{
- gen_op_mov_TN_reg(OT_LONG, 0, reg);
+ gen_op_mov_TN_reg(MO_32, 0, reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_LONG, reg);
+ gen_op_mov_reg_T0(MO_32, reg);
}
break;
case 0xd6: /* salc */
@@ -7314,7 +7306,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_compute_eflags_c(s, cpu_T[0]);
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(OT_BYTE, R_EAX);
+ gen_op_mov_reg_T0(MO_8, R_EAX);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
@@ -7323,7 +7315,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int l1, l2, l3;
- tval = (int8_t)insn_get(env, s, OT_BYTE);
+ tval = (int8_t)insn_get(env, s, MO_8);
next_eip = s->pc - s->cs_base;
tval += next_eip;
if (s->dflag == 0)
@@ -7464,7 +7456,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
- ot = OT_WORD;
+ ot = MO_16;
if (mod == 3)
ot += s->dflag;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
@@ -7476,7 +7468,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lldt(cpu_env, cpu_tmp2_i32);
@@ -7487,7 +7479,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
- ot = OT_WORD;
+ ot = MO_16;
if (mod == 3)
ot += s->dflag;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
@@ -7499,7 +7491,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_ltr(cpu_env, cpu_tmp2_i32);
@@ -7509,7 +7501,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 5: /* verw */
if (!s->pe || s->vm86)
goto illegal_op;
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_update_cc_op(s);
if (op == 4) {
gen_helper_verr(cpu_env, cpu_T[0]);
@@ -7534,12 +7526,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(s, CODE64(s) + OT_LONG);
+ gen_op_st_T0_A0(s, CODE64(s) + MO_32);
break;
case 1:
if (mod == 3) {
@@ -7597,12 +7589,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
- gen_op_st_T0_A0(s, OT_WORD);
+ gen_op_st_T0_A0(s, MO_16);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(s, CODE64(s) + OT_LONG);
+ gen_op_st_T0_A0(s, CODE64(s) + MO_32);
}
break;
case 2: /* lgdt */
@@ -7697,9 +7689,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(s, OT_WORD);
+ gen_op_ld_T1_A0(s, MO_16);
gen_add_A0_im(s, 2);
- gen_op_ld_T0_A0(s, CODE64(s) + OT_LONG);
+ gen_op_ld_T0_A0(s, CODE64(s) + MO_32);
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
if (op == 2) {
@@ -7718,14 +7710,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
#else
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
#endif
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1);
break;
case 6: /* lmsw */
if (s->cpl != 0) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_helper_lmsw(cpu_env, cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -7802,7 +7794,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s)) {
int d_ot;
/* d_ot is the size of destination */
- d_ot = dflag + OT_WORD;
+ d_ot = dflag + MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -7810,17 +7802,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(OT_LONG, 0, rm);
+ gen_op_mov_TN_reg(MO_32, 0, rm);
/* sign extend */
- if (d_ot == OT_QUAD)
+ if (d_ot == MO_64)
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(d_ot, reg);
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- if (d_ot == OT_QUAD) {
- gen_op_lds_T0_A0(s, OT_LONG);
+ if (d_ot == MO_64) {
+ gen_op_lds_T0_A0(s, MO_32);
} else {
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -7835,7 +7827,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
t2 = tcg_temp_local_new();
- ot = OT_WORD;
+ ot = MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7880,10 +7872,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGv t0;
if (!s->pe || s->vm86)
goto illegal_op;
- ot = dflag ? OT_LONG : OT_WORD;
+ ot = dflag ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
- gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
t0 = tcg_temp_local_new();
gen_update_cc_op(s);
if (b == 0x102) {
@@ -7937,9 +7929,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | rex_r;
if (CODE64(s))
- ot = OT_QUAD;
+ ot = MO_64;
else
- ot = OT_LONG;
+ ot = MO_32;
if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
(s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
reg = 8;
@@ -7982,9 +7974,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | rex_r;
if (CODE64(s))
- ot = OT_QUAD;
+ ot = MO_64;
else
- ot = OT_LONG;
+ ot = MO_32;
/* XXX: do it dynamically with CR4.DE bit */
if (reg == 4 || reg == 5 || reg >= 8)
goto illegal_op;
@@ -8016,7 +8008,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c3: /* MOVNTI reg, mem */
if (!(s->cpuid_features & CPUID_SSE2))
goto illegal_op;
- ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ ot = s->dflag == 2 ? MO_64 : MO_32;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -8068,12 +8060,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op == 2) {
- gen_op_ld_T0_A0(s, OT_LONG);
+ gen_op_ld_T0_A0(s, MO_32);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
- gen_op_st_T0_A0(s, OT_LONG);
+ gen_op_st_T0_A0(s, MO_32);
}
break;
case 5: /* lfence */
@@ -8126,11 +8118,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
if (s->prefix & PREFIX_DATA)
- ot = OT_WORD;
+ ot = MO_16;
else if (s->dflag != 2)
- ot = OT_LONG;
+ ot = MO_32;
else
- ot = OT_QUAD;
+ ot = MO_64;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 07/60] target-i386: Remove gen_op_ld_T0_A0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (5 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 06/60] target-i386: Replace OT_* constants with MO_* constants Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 08/60] target-i386: Remove gen_op_ldu_T0_A0 Richard Henderson
` (53 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
Propagate its definition into all users.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 77 +++++++++++++++++++++++--------------------------
1 file changed, 36 insertions(+), 41 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 87f4470..8e231b3 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,12 +586,6 @@ static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-/* XXX: always use ldu or lds */
-static inline void gen_op_ld_T0_A0(DisasContext *s, int idx)
-{
- gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
-}
-
static inline void gen_op_ldu_T0_A0(DisasContext *s, int idx)
{
gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
@@ -811,7 +805,7 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
static inline void gen_movs(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_string_movl_A0_EDI(s);
gen_op_st_T0_A0(s, ot);
gen_op_movl_T0_Dshift(ot);
@@ -1246,7 +1240,7 @@ static inline void gen_stos(DisasContext *s, int ot)
static inline void gen_lods(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
@@ -1297,7 +1291,7 @@ static inline void gen_outs(DisasContext *s, int ot)
if (use_icount)
gen_io_start();
gen_string_movl_A0_ESI(s);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_TN_reg(MO_16, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
@@ -1417,7 +1411,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
} else {
- gen_op_ld_T0_A0(s1, ot);
+ gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
switch(op) {
case OP_ADCL:
@@ -1501,10 +1495,11 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
/* if d == OR_TMP0, it means memory operand (address in A0) */
static void gen_inc(DisasContext *s1, int ot, int d, int c)
{
- if (d != OR_TMP0)
+ if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
- else
- gen_op_ld_T0_A0(s1, ot);
+ } else {
+ gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
+ }
gen_compute_eflags_c(s1, cpu_cc_src);
if (c > 0) {
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
@@ -1572,7 +1567,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1612,7 +1607,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
gen_op_mov_TN_reg(ot, 0, op1);
@@ -1663,7 +1658,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1753,7 +1748,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -1835,7 +1830,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
gen_op_mov_TN_reg(ot, 0, op1);
@@ -1890,7 +1885,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, op1);
}
@@ -2309,7 +2304,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_st_T0_A0(s, ot);
} else {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
if (reg != OR_TMP0)
gen_op_mov_reg_T0(ot, reg);
}
@@ -2588,7 +2583,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_T0_A0(s, s->dflag ? MO_64 : MO_16);
+ gen_op_ld_v(s, s->dflag ? MO_64 : MO_16, cpu_T[0], cpu_A0);
} else
#endif
{
@@ -2600,7 +2595,7 @@ static void gen_pop_T0(DisasContext *s)
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_ld_T0_A0(s, s->dflag + 1);
+ gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
}
}
@@ -2659,7 +2654,7 @@ static void gen_popa(DisasContext *s)
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_T0_A0(s, MO_16 + s->dflag);
+ gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i);
}
gen_op_addl_A0_im(2 << s->dflag);
@@ -3345,7 +3340,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x210: /* movss xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_movl_T0_0();
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
@@ -3709,7 +3704,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if ((b >> 8) & 1) {
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
}
op2_offset = offsetof(CPUX86State,xmm_t0);
@@ -4528,7 +4523,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* specific case for SSE single instructions */
if (b1 == 2) {
/* 32 bit access */
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
} else {
/* 64 bit access */
@@ -4932,7 +4927,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (op == 0)
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -5144,7 +5139,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op >= 2 && op != 3 && op != 5)
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -5767,7 +5762,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(ot, R_EAX);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
@@ -6010,12 +6005,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6049,12 +6044,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
switch(op >> 4) {
case 0:
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -6128,7 +6123,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
break;
case 0x0d: /* fldcw mem */
- gen_op_ld_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
break;
@@ -6735,7 +6730,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_T0_A0(s, 1 + s->dflag);
+ gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0);
if (s->dflag == 0)
gen_op_andl_T0_ffff();
/* NOTE: keeping EIP updated is not a problem in case of
@@ -6743,7 +6738,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_jmp_T0();
/* pop selector */
gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_T0_A0(s, 1 + s->dflag);
+ gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
gen_stack_update(s, val + (4 << s->dflag));
@@ -6990,7 +6985,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
s->rip_offset = 1;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -7026,7 +7021,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- gen_op_ld_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
}
@@ -7691,7 +7686,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_op_ld_T1_A0(s, MO_16);
gen_add_A0_im(s, 2);
- gen_op_ld_T0_A0(s, CODE64(s) + MO_32);
+ gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
if (op == 2) {
@@ -7812,7 +7807,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (d_ot == MO_64) {
gen_op_lds_T0_A0(s, MO_32);
} else {
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -8060,7 +8055,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (op == 2) {
- gen_op_ld_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 08/60] target-i386: Remove gen_op_ldu_T0_A0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (6 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 07/60] target-i386: Remove gen_op_ld_T0_A0 Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 09/60] target-i386: Remove gen_op_ld_T1_A0 Richard Henderson
` (52 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
Propagate its definition into all users.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8e231b3..c64203e 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,11 +586,6 @@ static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-static inline void gen_op_ldu_T0_A0(DisasContext *s, int idx)
-{
- gen_op_ld_v(s, idx, cpu_T[0], cpu_A0);
-}
-
static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
{
gen_op_ld_v(s, idx, cpu_T[1], cpu_A0);
@@ -5172,7 +5167,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3: /* lcall Ev */
gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
- gen_op_ldu_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_lcall:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5198,7 +5193,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 5: /* ljmp Ev */
gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
- gen_op_ldu_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_ljmp:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
@@ -5711,7 +5706,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (b & 8) {
gen_op_lds_T0_A0(s, ot);
} else {
- gen_op_ldu_T0_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
}
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -5790,7 +5785,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
}
gen_add_A0_ds_seg(s);
- gen_op_ldu_T0_A0(s, MO_8);
+ gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(MO_8, R_EAX);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
@@ -5881,7 +5876,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_T1_A0(s, ot);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
/* load the segment first to handle exceptions properly */
- gen_op_ldu_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
gen_op_mov_reg_T1(ot, reg);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 09/60] target-i386: Remove gen_op_ld_T1_A0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (7 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 08/60] target-i386: Remove gen_op_ldu_T0_A0 Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 10/60] target-i386: Remove gen_op_lds_T0_A0 Richard Henderson
` (51 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
Propagate its definition into all users.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 23 +++++++++--------------
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c64203e..586e5af 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,11 +586,6 @@ static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
-{
- gen_op_ld_v(s, idx, cpu_T[1], cpu_A0);
-}
-
static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
@@ -1244,7 +1239,7 @@ static inline void gen_lods(DisasContext *s, int ot)
static inline void gen_scas(DisasContext *s, int ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1253,7 +1248,7 @@ static inline void gen_scas(DisasContext *s, int ot)
static inline void gen_cmps(DisasContext *s, int ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
@@ -4834,7 +4829,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
@@ -5165,7 +5160,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 3: /* lcall Ev */
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_lcall:
@@ -5191,7 +5186,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 5: /* ljmp Ev */
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_ljmp:
@@ -5356,7 +5351,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_addl_T0_T1();
gen_op_st_T0_A0(s, ot);
gen_op_mov_reg_T1(ot, reg);
@@ -5842,7 +5837,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_st_T0_A0(s, ot);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
@@ -5873,7 +5868,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(s, ot);
+ gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
/* load the segment first to handle exceptions properly */
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
@@ -7679,7 +7674,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T1_A0(s, MO_16);
+ gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
if (!s->dflag)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 10/60] target-i386: Remove gen_op_lds_T0_A0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (8 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 09/60] target-i386: Remove gen_op_ld_T1_A0 Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 11/60] target-i386: Introduce gen_op_st_rm_T0_A0 Richard Henderson
` (50 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
Replace its users by gen_op_ld_v with the MO_SIGN bit set.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 586e5af..8c3d7ae 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -576,11 +576,6 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
}
#endif
-static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
-{
- tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0, s->mem_index, idx | MO_LE | MO_SIGN);
-}
-
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
@@ -5699,7 +5694,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (b & 8) {
- gen_op_lds_T0_A0(s, ot);
+ gen_op_ld_v(s, ot | MO_SIGN, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
}
@@ -6011,7 +6006,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
@@ -6050,7 +6045,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_lds_T0_A0(s, MO_16);
+ gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
@@ -7795,7 +7790,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
if (d_ot == MO_64) {
- gen_op_lds_T0_A0(s, MO_32);
+ gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 11/60] target-i386: Introduce gen_op_st_rm_T0_A0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (9 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 10/60] target-i386: Remove gen_op_lds_T0_A0 Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 12/60] target-i386: Remove gen_op_st_T0_A0 Richard Henderson
` (49 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
Too many places have the same test vs OR_TMP0 to indicate
a write back to memory. Hoist that to a subroutine.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 85 ++++++++++++++-----------------------------------
1 file changed, 24 insertions(+), 61 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8c3d7ae..268ed84 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -596,6 +596,15 @@ static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
gen_op_st_v(s, idx, cpu_T[1], cpu_A0);
}
+static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
+{
+ if (d == OR_TMP0) {
+ gen_op_st_T0_A0(s, idx);
+ } else {
+ gen_op_mov_reg_T0(idx, d);
+ }
+}
+
static inline void gen_jmp_im(target_ulong pc)
{
tcg_gen_movi_tl(cpu_tmp0, pc);
@@ -1403,10 +1412,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
gen_compute_eflags_c(s1, cpu_tmp4);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_ADCB + ot);
break;
@@ -1414,57 +1420,39 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
gen_compute_eflags_c(s1, cpu_tmp4);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_SBBB + ot);
break;
case OP_ADDL:
gen_op_addl_T0_T1();
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_ADDB + ot);
break;
case OP_SUBL:
tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_SUBB + ot);
break;
default:
case OP_ANDL:
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
case OP_ORL:
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
case OP_XORL:
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
@@ -1493,10 +1481,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
set_cc_op(s1, CC_OP_DECB + ot);
}
- if (d != OR_TMP0)
- gen_op_mov_reg_T0(ot, d);
- else
- gen_op_st_T0_A0(s1, ot);
+ gen_op_st_rm_T0_A0(s1, ot, d);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
@@ -1576,11 +1561,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
}
/* store */
- if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(s, ot);
- } else {
- gen_op_mov_reg_T0(ot, op1);
- }
+ gen_op_st_rm_T0_A0(s, ot, op1);
gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, cpu_T[1], is_right);
}
@@ -1615,11 +1596,8 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
}
/* store */
- if (op1 == OR_TMP0)
- gen_op_st_T0_A0(s, ot);
- else
- gen_op_mov_reg_T0(ot, op1);
-
+ gen_op_st_rm_T0_A0(s, ot, op1);
+
/* update eflags if non zero shift */
if (op2 != 0) {
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
@@ -1683,11 +1661,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
}
/* store */
- if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(s, ot);
- } else {
- gen_op_mov_reg_T0(ot, op1);
- }
+ gen_op_st_rm_T0_A0(s, ot, op1);
/* We'll need the flags computed into CC_SRC. */
gen_compute_eflags(s);
@@ -1778,11 +1752,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
}
/* store */
- if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(s, ot);
- } else {
- gen_op_mov_reg_T0(ot, op1);
- }
+ gen_op_st_rm_T0_A0(s, ot, op1);
if (op2 != 0) {
/* Compute the flags into CC_SRC. */
@@ -1855,10 +1825,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
}
}
/* store */
- if (op1 == OR_TMP0)
- gen_op_st_T0_A0(s, ot);
- else
- gen_op_mov_reg_T0(ot, op1);
+ gen_op_st_rm_T0_A0(s, ot, op1);
}
/* XXX: add faster immediate case */
@@ -1937,11 +1904,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
}
/* store */
- if (op1 == OR_TMP0) {
- gen_op_st_T0_A0(s, ot);
- } else {
- gen_op_mov_reg_T0(ot, op1);
- }
+ gen_op_st_rm_T0_A0(s, ot, op1);
gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, count, is_right);
tcg_temp_free(count);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 12/60] target-i386: Remove gen_op_st_T0_A0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (10 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 11/60] target-i386: Introduce gen_op_st_rm_T0_A0 Richard Henderson
@ 2013-11-29 2:59 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 13/60] target-i386: Remove gen_op_st_T1_A0 Richard Henderson
` (48 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 2:59 UTC (permalink / raw)
To: qemu-devel
Propagate its definition into all users.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 83 ++++++++++++++++++++++++-------------------------
1 file changed, 40 insertions(+), 43 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 268ed84..d3fc8f3 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,11 +586,6 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-static inline void gen_op_st_T0_A0(DisasContext *s, int idx)
-{
- gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
-}
-
static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
{
gen_op_st_v(s, idx, cpu_T[1], cpu_A0);
@@ -599,7 +594,7 @@ static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
{
if (d == OR_TMP0) {
- gen_op_st_T0_A0(s, idx);
+ gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
} else {
gen_op_mov_reg_T0(idx, d);
}
@@ -801,7 +796,7 @@ static inline void gen_movs(DisasContext *s, int ot)
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_string_movl_A0_EDI(s);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1226,7 +1221,7 @@ static inline void gen_stos(DisasContext *s, int ot)
{
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
gen_string_movl_A0_EDI(s);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
@@ -1268,12 +1263,12 @@ static inline void gen_ins(DisasContext *s, int ot)
/* Note: we must do this dummy write first to be restartable in
case of page fault. */
gen_op_movl_T0_0();
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_TN_reg(MO_16, 1, R_EDX);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
if (use_icount)
@@ -2250,7 +2245,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
if (reg != OR_TMP0)
@@ -2453,10 +2448,10 @@ static void gen_push_T0(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T0_A0(s, MO_64);
+ gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2477,7 +2472,7 @@ static void gen_push_T0(DisasContext *s)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_T0_A0(s, s->dflag + 1);
+ gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
else
@@ -2497,7 +2492,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_st_T1_A0(s, MO_64);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
@@ -2582,7 +2577,7 @@ static void gen_pusha(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(MO_32, 0, 7 - i);
- gen_op_st_T0_A0(s, MO_16 + s->dflag);
+ gen_op_st_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
gen_op_addl_A0_im(2 << s->dflag);
}
gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
@@ -2626,7 +2621,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
/* push bp */
gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (level) {
/* XXX: must save state */
gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
@@ -2651,7 +2646,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
gen_op_addl_A0_seg(s, R_SS);
/* push bp */
gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (level) {
/* XXX: must save state */
gen_helper_enter_level(cpu_env, tcg_const_i32(level),
@@ -3223,7 +3218,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
}
break;
case 0x6e: /* movd mm, ea */
@@ -3475,7 +3470,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
@@ -4890,7 +4885,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 2: /* not */
tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
if (mod != 3) {
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_reg_T0(ot, rm);
}
@@ -4898,7 +4893,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3: /* neg */
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
if (mod != 3) {
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_reg_T0(ot, rm);
}
@@ -5311,7 +5306,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_addl_T0_T1();
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T1(ot, reg);
}
gen_op_update2_cc();
@@ -5570,10 +5565,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
val = insn_get(env, s, ot);
gen_op_movl_T0_im(val);
- if (mod != 3)
- gen_op_st_T0_A0(s, ot);
- else
+ if (mod != 3) {
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ } else {
gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
+ }
break;
case 0x8a:
case 0x8b: /* mov Ev, Gv */
@@ -5714,7 +5710,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(ot, R_EAX);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
}
}
break;
@@ -5796,7 +5792,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_op_st_T0_A0(s, ot);
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
gen_op_mov_reg_T1(ot, reg);
@@ -6020,7 +6016,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 1:
gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
@@ -6031,7 +6027,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
break;
}
gen_helper_fpop(cpu_env);
@@ -6041,12 +6037,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
break;
case 1:
gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
@@ -6057,7 +6053,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
default:
gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
break;
}
if ((op & 7) == 3)
@@ -6083,7 +6079,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
break;
case 0x1d: /* fldt mem */
gen_update_cc_op(s);
@@ -6109,7 +6105,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
break;
case 0x3c: /* fbld */
gen_update_cc_op(s);
@@ -7003,10 +6999,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
set_cc_op(s, CC_OP_SARB + ot);
if (op != 0) {
- if (mod != 3)
- gen_op_st_T0_A0(s, ot);
- else
+ if (mod != 3) {
+ gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ } else {
gen_op_mov_reg_T0(ot, rm);
+ }
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_movi_tl(cpu_cc_dst, 0);
}
@@ -7469,12 +7466,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(s, CODE64(s) + MO_32);
+ gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
break;
case 1:
if (mod == 3) {
@@ -7532,12 +7529,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
- gen_op_st_T0_A0(s, MO_16);
+ gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
if (!s->dflag)
gen_op_andl_T0_im(0xffffff);
- gen_op_st_T0_A0(s, CODE64(s) + MO_32);
+ gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
}
break;
case 2: /* lgdt */
@@ -8008,7 +8005,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
- gen_op_st_T0_A0(s, MO_32);
+ gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
}
break;
case 5: /* lfence */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 13/60] target-i386: Remove gen_op_st_T1_A0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (11 preceding siblings ...)
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 12/60] target-i386: Remove gen_op_st_T0_A0 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 14/60] target-i386: Fix typo in gen_push_T1 Richard Henderson
` (47 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Propagate its definition into all users.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index d3fc8f3..b28663b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,11 +586,6 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE);
}
-static inline void gen_op_st_T1_A0(DisasContext *s, int idx)
-{
- gen_op_st_v(s, idx, cpu_T[1], cpu_A0);
-}
-
static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
{
if (d == OR_TMP0) {
@@ -2489,7 +2484,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_movq_A0_reg(R_ESP);
if (s->dflag) {
gen_op_addq_A0_im(-8);
- gen_op_st_T1_A0(s, MO_64);
+ gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
} else {
gen_op_addq_A0_im(-2);
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
@@ -2511,7 +2506,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_T1_A0(s, s->dflag + 1);
+ gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(1, R_ESP);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 14/60] target-i386: Fix typo in gen_push_T1
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (12 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 13/60] target-i386: Remove gen_op_st_T1_A0 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 15/60] target-i386: Tidy mov[sz][bw] Richard Henderson
` (46 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
By inspection, obviously we should be storing T[1] not T[0].
This could only happen for x86_64 in 64-bit mode with 0x66
prefix to call insn -- i.e. never.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index b28663b..c1591d9 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2487,7 +2487,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
} else {
gen_op_addq_A0_im(-2);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0);
}
gen_op_mov_reg_A0(2, R_ESP);
} else
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 15/60] target-i386: Tidy mov[sz][bw]
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (13 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 14/60] target-i386: Fix typo in gen_push_T1 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 16/60] target-i386: Tidy movsl Richard Henderson
` (45 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
We can use the MO_SIGN bit to tidy the reg-reg switch statement
as well as pass it on to gen_op_ld_v, eliminating one call.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c1591d9..47ed0b4 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -5617,11 +5617,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1be: /* movsbS Gv, Eb */
case 0x1bf: /* movswS Gv, Eb */
{
- int d_ot;
+ TCGMemOp d_ot;
+ TCGMemOp s_ot;
+
/* d_ot is the size of destination */
d_ot = dflag + MO_16;
/* ot is the size of source */
ot = (b & 1) + MO_8;
+ /* s_ot is the sign+size of source */
+ s_ot = b & 8 ? MO_SIGN | ot : ot;
+
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5629,29 +5634,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3) {
gen_op_mov_TN_reg(ot, 0, rm);
- switch(ot | (b & 8)) {
- case MO_8:
+ switch (s_ot) {
+ case MO_UB:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
break;
- case MO_8 | 8:
+ case MO_SB:
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
break;
- case MO_16:
+ case MO_UW:
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
break;
default:
- case MO_16 | 8:
+ case MO_SW:
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
gen_op_mov_reg_T0(d_ot, reg);
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- if (b & 8) {
- gen_op_ld_v(s, ot | MO_SIGN, cpu_T[0], cpu_A0);
- } else {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- }
+ gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 16/60] target-i386: Tidy movsl
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (14 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 15/60] target-i386: Tidy mov[sz][bw] Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 17/60] target-i386: Remove unused arguments to gen_lea_modrm Richard Henderson
` (44 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Always perform a sign-extending load. In the extremely unlikely
case that we've used an 0x66 prefix, the extension to 64-bits is
unnecessary but not wrong; the store will still examine only 16 bits.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 47ed0b4..d919c74 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7745,11 +7745,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(d_ot, reg);
} else {
gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- if (d_ot == MO_64) {
- gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
- } else {
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- }
+ gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
} else
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 17/60] target-i386: Remove unused arguments to gen_lea_modrm
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (15 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 16/60] target-i386: Tidy movsl Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 18/60] target-i386: Use MO_BE for movbe Richard Henderson
` (43 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
The reg_ptr and offset_ptr outputs are universally unused.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 146 +++++++++++++++++++++++-------------------------
1 file changed, 69 insertions(+), 77 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index d919c74..45a00ba 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1957,15 +1957,13 @@ static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
}
}
-static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
- int *reg_ptr, int *offset_ptr)
+static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
{
target_long disp;
int havesib;
int base;
int index;
int scale;
- int opreg;
int mod, rm, code, override, must_add_seg;
TCGv sum;
@@ -2060,7 +2058,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- goto done;
+ return;
}
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
@@ -2136,12 +2134,6 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
gen_op_addl_A0_seg(s, override);
}
}
-
- done:
- opreg = OR_A0;
- disp = 0;
- *reg_ptr = opreg;
- *offset_ptr = disp;
}
static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
@@ -2221,7 +2213,7 @@ static void gen_add_A0_ds_seg(DisasContext *s)
static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
int ot, int reg, int is_store)
{
- int mod, rm, opreg, disp;
+ int mod, rm;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
@@ -2236,7 +2228,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
gen_op_mov_reg_T0(ot, reg);
}
} else {
- gen_lea_modrm(env, s, modrm, &opreg, &disp);
+ gen_lea_modrm(env, s, modrm);
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
@@ -3115,7 +3107,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
target_ulong pc_start, int rex_r)
{
int b1, op1_offset, op2_offset, is_xmm, val, ot;
- int modrm, mod, rm, reg, reg_addr, offset_addr;
+ int modrm, mod, rm, reg;
SSEFunc_0_epp sse_fn_epp;
SSEFunc_0_eppi sse_fn_eppi;
SSEFunc_0_ppi sse_fn_ppi;
@@ -3186,7 +3178,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x0e7: /* movntq */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
break;
case 0x1e7: /* movntdq */
@@ -3194,20 +3186,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x12b: /* movntps */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
break;
case 0x3f0: /* lddqu */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
break;
case 0x22b: /* movntss */
case 0x32b: /* movntsd */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
if (b1 & 1) {
gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
@@ -3250,7 +3242,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x6f: /* movq mm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
@@ -3267,7 +3259,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x16f: /* movdqa xmm, ea */
case 0x26f: /* movdqu xmm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3277,7 +3269,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x210: /* movss xmm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_movl_T0_0();
@@ -3292,7 +3284,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x310: /* movsd xmm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
gen_op_movl_T0_0();
@@ -3307,7 +3299,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x012: /* movlps */
case 0x112: /* movlpd */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3319,7 +3311,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x212: /* movsldup */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3335,7 +3327,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x312: /* movddup */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3349,7 +3341,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x016: /* movhps */
case 0x116: /* movhpd */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(1)));
} else {
@@ -3361,7 +3353,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x216: /* movshdup */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3426,7 +3418,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x27e: /* movq xmm, ea */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3438,7 +3430,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x7f: /* movq ea, mm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
} else {
rm = (modrm & 7);
@@ -3453,7 +3445,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x17f: /* movdqa ea, xmm */
case 0x27f: /* movdqu ea, xmm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
rm = (modrm & 7) | REX_B(s);
@@ -3463,7 +3455,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x211: /* movss ea, xmm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
} else {
@@ -3474,7 +3466,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x311: /* movsd ea, xmm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3486,7 +3478,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x013: /* movlps */
case 0x113: /* movlpd */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3496,7 +3488,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x017: /* movhps */
case 0x117: /* movhpd */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(1)));
} else {
@@ -3562,7 +3554,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x12a: /* cvtpi2pd */
gen_helper_enter_mmx(cpu_env);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,mmx_t0);
gen_ldq_env_A0(s, op2_offset);
} else {
@@ -3607,7 +3599,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x12d: /* cvtpd2pi */
gen_helper_enter_mmx(cpu_env);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,xmm_t0);
gen_ldo_env_A0(s, op2_offset);
} else {
@@ -3638,7 +3630,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x32d: /* cvtsd2si */
ot = (s->dflag == 2) ? MO_64 : MO_32;
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
if ((b >> 8) & 1) {
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
@@ -3704,7 +3696,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
} else {
@@ -3772,7 +3764,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
} else {
op2_offset = offsetof(CPUX86State,xmm_t0);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
switch (b) {
case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
@@ -3806,7 +3798,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
} else {
op2_offset = offsetof(CPUX86State,mmx_t0);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, op2_offset);
}
}
@@ -4239,7 +4231,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = (s->dflag == 2) ? MO_64 : MO_32;
rm = (modrm & 7) | REX_B(s);
if (mod != 3)
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
reg = ((modrm >> 3) & 7) | rex_r;
val = cpu_ldub_code(env, s->pc++);
switch (b) {
@@ -4378,7 +4370,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
} else {
op2_offset = offsetof(CPUX86State,xmm_t0);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, op2_offset);
}
} else {
@@ -4387,7 +4379,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
} else {
op2_offset = offsetof(CPUX86State,mmx_t0);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, op2_offset);
}
}
@@ -4454,7 +4446,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (is_xmm) {
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,xmm_t0);
if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
b == 0xc2)) {
@@ -4478,7 +4470,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,mmx_t0);
gen_ldq_env_A0(s, op2_offset);
} else {
@@ -4560,7 +4552,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int b, prefixes, aflag, dflag;
int shift, ot;
- int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
+ int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
@@ -4755,7 +4747,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else if (op == OP_XORL && rm == reg) {
xor_zero:
@@ -4776,7 +4768,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
@@ -4818,7 +4810,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->rip_offset = 1;
else
s->rip_offset = insn_const_size(ot);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = rm;
@@ -4864,7 +4856,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
if (op == 0)
s->rip_offset = insn_const_size(ot);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
@@ -5075,7 +5067,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
}
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
if (op >= 2 && op != 3 && op != 5)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
@@ -5297,7 +5289,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T1(ot, reg);
gen_op_mov_reg_T0(ot, rm);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_addl_T0_T1();
@@ -5329,7 +5321,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
gen_op_mov_v_reg(ot, t0, rm);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
tcg_gen_mov_tl(a0, cpu_A0);
gen_op_ld_v(s, ot, t0, a0);
rm = 0; /* avoid warning */
@@ -5377,7 +5369,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_jmp_im(pc_start - s->cs_base);
gen_update_cc_op(s);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_helper_cmpxchg16b(cpu_env, cpu_A0);
} else
#endif
@@ -5386,7 +5378,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_jmp_im(pc_start - s->cs_base);
gen_update_cc_op(s);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_helper_cmpxchg8b(cpu_env, cpu_A0);
}
set_cc_op(s, CC_OP_EFLAGS);
@@ -5556,7 +5548,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod != 3) {
s->rip_offset = insn_const_size(ot);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
}
val = insn_get(env, s, ot);
gen_op_movl_T0_im(val);
@@ -5651,7 +5643,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
gen_op_mov_reg_T0(d_ot, reg);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -5669,7 +5661,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->override = -1;
val = s->addseg;
s->addseg = 0;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
s->addseg = val;
gen_op_mov_reg_A0(ot - MO_16, reg);
break;
@@ -5782,7 +5774,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(ot, rm);
gen_op_mov_reg_T1(ot, reg);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
@@ -5817,7 +5809,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
/* load the segment first to handle exceptions properly */
@@ -5852,7 +5844,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (shift == 2) {
s->rip_offset = 1;
}
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = (modrm & 7) | REX_B(s);
@@ -5902,7 +5894,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
reg = ((modrm >> 3) & 7) | rex_r;
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
opreg = OR_TMP0;
} else {
opreg = rm;
@@ -5933,7 +5925,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = ((b & 7) << 3) | ((modrm >> 3) & 7);
if (mod != 3) {
/* memory op */
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
switch(op) {
case 0x00 ... 0x07: /* fxxxs */
case 0x10 ... 0x17: /* fixxxl */
@@ -6924,7 +6916,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
s->rip_offset = 1;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
@@ -6955,7 +6947,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
gen_op_mov_TN_reg(MO_32, 1, reg);
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
/* specific case: we need to add a displacement */
gen_exts(ot, cpu_T[1]);
tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
@@ -7212,7 +7204,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_op_mov_TN_reg(ot, 0, reg);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
if (ot == MO_16) {
@@ -7460,7 +7452,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
@@ -7523,7 +7515,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
} else { /* sidt */
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
@@ -7624,7 +7616,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
@@ -7666,7 +7658,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_helper_invlpg(cpu_env, cpu_A0);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -7744,7 +7736,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(d_ot, reg);
} else {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(d_ot, reg);
}
@@ -7765,7 +7757,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
rm = modrm & 7;
if (mod != 3) {
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, t0, cpu_A0);
a0 = tcg_temp_local_new();
tcg_gen_mov_tl(a0, cpu_A0);
@@ -7835,7 +7827,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3: /* prefetchnt0 */
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
/* nothing more to do */
break;
default: /* nop (multi byte) */
@@ -7962,7 +7954,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
break;
}
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
@@ -7975,7 +7967,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
break;
}
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_fxrstor(cpu_env, cpu_A0,
@@ -7990,7 +7982,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
if (op == 2) {
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -8015,7 +8007,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* clflush */
if (!(s->cpuid_features & CPUID_CLFLUSH))
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
}
break;
default:
@@ -8027,7 +8019,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
+ gen_lea_modrm(env, s, modrm);
/* ignore for now */
break;
case 0x1aa: /* rsm */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 18/60] target-i386: Use MO_BE for movbe
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (16 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 17/60] target-i386: Remove unused arguments to gen_lea_modrm Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 19/60] target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32 Richard Henderson
` (42 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Fold the bswap into the memory operation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 40 +++++-----------------------------------
1 file changed, 5 insertions(+), 35 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 45a00ba..107f0e6 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3868,44 +3868,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = MO_64;
}
- /* Load the data incoming to the bswap. Note that the TCG
- implementation of bswap requires the input be zero
- extended. In the case of the loads, we simply know that
- gen_op_ld_v via gen_ldst_modrm does that already. */
- if ((b & 1) == 0) {
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- } else {
- switch (ot) {
- case MO_16:
- tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[reg]);
- break;
- default:
- tcg_gen_ext32u_tl(cpu_T[0], cpu_regs[reg]);
- break;
- case MO_64:
- tcg_gen_mov_tl(cpu_T[0], cpu_regs[reg]);
- break;
- }
- }
-
- switch (ot) {
- case MO_16:
- tcg_gen_bswap16_tl(cpu_T[0], cpu_T[0]);
- break;
- default:
- tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- break;
-#ifdef TARGET_X86_64
- case MO_64:
- tcg_gen_bswap64_tl(cpu_T[0], cpu_T[0]);
- break;
-#endif
- }
-
+ gen_lea_modrm(env, s, modrm);
if ((b & 1) == 0) {
+ tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
+ s->mem_index, ot | MO_BE);
gen_op_mov_reg_T0(ot, reg);
} else {
- gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
+ tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0,
+ s->mem_index, ot | MO_BE);
}
break;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 19/60] target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (17 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 18/60] target-i386: Use MO_BE for movbe Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 20/60] target-i386: Tidy load + truncate Richard Henderson
` (41 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
For the 16 and 32-bit cases, we don't need to truncate via
a temporary register.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 107f0e6..16fae82 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1259,8 +1259,7 @@ static inline void gen_ins(DisasContext *s, int ot)
case of page fault. */
gen_op_movl_T0_0();
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_TN_reg(MO_16, 1, R_EDX);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
@@ -1277,8 +1276,7 @@ static inline void gen_outs(DisasContext *s, int ot)
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_TN_reg(MO_16, 1, R_EDX);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
@@ -3838,8 +3836,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = MO_64;
}
- gen_op_mov_TN_reg(MO_32, 0, reg);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[reg]);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
cpu_T[0], tcg_const_i32(8 << ot));
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 20/60] target-i386: Tidy load + truncate
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (18 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 19/60] target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 21/60] target-i386: Tidy extend + store Richard Henderson
` (40 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
We can now use tcg_gen_qemu_ld_i32 directly to avoid the truncation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 39 +++++++++++++++++++--------------------
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 16fae82..117714d 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4302,12 +4302,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x22:
if (ot == MO_32) { /* pinsrd */
if (mod == 3) {
- gen_op_mov_v_reg(ot, cpu_tmp0, rm);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[rm]);
} else {
- tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
- s->mem_index, MO_LEUL);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
}
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
@@ -5904,13 +5903,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
case 2:
@@ -5920,8 +5919,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LESW);
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
}
@@ -5943,13 +5942,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
switch(op >> 4) {
case 0:
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
break;
case 1:
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
case 2:
@@ -5959,8 +5958,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3:
default:
- gen_op_ld_v(s, MO_SW, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LESW);
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
}
@@ -6022,8 +6021,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
break;
case 0x0d: /* fldcw mem */
- gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
break;
case 0x0e: /* fnstenv mem */
@@ -7951,8 +7950,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm);
if (op == 2) {
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 21/60] target-i386: Tidy extend + store
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (19 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 20/60] target-i386: Tidy load + truncate Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 22/60] target-i386: Tidy extend + move Richard Henderson
` (39 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
We can now use tcg_gen_qemu_st_i32 directly to avoid the extension.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 117714d..7917eca 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4227,12 +4227,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
if (mod == 3) {
+ tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
- tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
- s->mem_index, MO_LEUL);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
}
} else { /* pextrq */
#ifdef TARGET_X86_64
@@ -5969,8 +5969,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 1:
gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
@@ -5980,8 +5980,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3:
default:
gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
break;
}
gen_helper_fpop(cpu_env);
@@ -5990,13 +5990,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op >> 4) {
case 0:
gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
break;
case 1:
gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUL);
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
@@ -6006,8 +6006,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 3:
default:
gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
break;
}
if ((op & 7) == 3)
@@ -6032,8 +6032,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
break;
case 0x1d: /* fldt mem */
gen_update_cc_op(s);
@@ -6058,8 +6058,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
+ s->mem_index, MO_LEUW);
break;
case 0x3c: /* fbld */
gen_update_cc_op(s);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 22/60] target-i386: Tidy extend + move
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (20 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 21/60] target-i386: Tidy extend + store Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 23/60] target-i386: Remove gen_op_movl_T0_0 Richard Henderson
` (38 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
For the known MO_32/MO_64 cases, we don't need to extend a 32-bit temp
into a 64-bit temp before storing into the hardware register.
We do need the extension for the MO_8/MO_16 cases, in order for the
deposit_tl operation to work, so leave those alone.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7917eca..51ee579 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3537,16 +3537,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(MO_32, reg);
+ tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
break;
case 0x150: /* movmskpd */
rm = (modrm & 7) | REX_B(s);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[rm]));
gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(MO_32, reg);
+ tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
break;
case 0x02a: /* cvtpi2ps */
case 0x12a: /* cvtpi2pd */
@@ -3730,9 +3728,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0);
}
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_T0(MO_32, reg);
+ tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
break;
case 0x138:
@@ -4228,8 +4225,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
if (mod == 3) {
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ tcg_gen_extu_i32_tl(cpu_regs[rm], cpu_tmp2_i32);
} else {
tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0,
s->mem_index, MO_LEUL);
@@ -4240,7 +4236,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
if (mod == 3) {
- gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
+ tcg_gen_mov_i64(cpu_regs[rm], cpu_tmp1_i64);
} else {
tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0,
s->mem_index, MO_LEQ);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 23/60] target-i386: Remove gen_op_movl_T0_0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (21 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 22/60] target-i386: Tidy extend + move Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 24/60] target-i386: Remove gen_op_movl_T0_im* Richard Henderson
` (37 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Propagate its definition into all users.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 51ee579..6f88ed9 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_T0_0(void)
-{
- tcg_gen_movi_tl(cpu_T[0], 0);
-}
-
static inline void gen_op_movl_T0_im(int32_t val)
{
tcg_gen_movi_tl(cpu_T[0], val);
@@ -1257,7 +1252,7 @@ static inline void gen_ins(DisasContext *s, int ot)
gen_string_movl_A0_EDI(s);
/* Note: we must do this dummy write first to be restartable in
case of page fault. */
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
@@ -3270,7 +3265,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
@@ -3285,7 +3280,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
} else {
@@ -3506,13 +3501,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (is_xmm) {
gen_op_movl_T0_im(val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
op1_offset = offsetof(CPUX86State,xmm_t0);
} else {
gen_op_movl_T0_im(val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
op1_offset = offsetof(CPUX86State,mmx_t0);
}
@@ -4715,7 +4710,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
xor_zero:
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
- gen_op_movl_T0_0();
+ tcg_gen_movi_tl(cpu_T[0], 0);
gen_op_mov_reg_T0(ot, reg);
break;
} else {
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 24/60] target-i386: Remove gen_op_movl_T0_im*
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (22 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 23/60] target-i386: Remove gen_op_movl_T0_0 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 25/60] " Richard Henderson
` (36 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Propagate the definition of gen_op_movl_T0_im to all users.
The function gen_op_movl_T0_imu was unused.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 32 ++++++++++----------------------
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6f88ed9..d836aee 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_T0_im(int32_t val)
-{
- tcg_gen_movi_tl(cpu_T[0], val);
-}
-
-static inline void gen_op_movl_T0_imu(uint32_t val)
-{
- tcg_gen_movi_tl(cpu_T[0], val);
-}
-
static inline void gen_op_movl_T1_im(int32_t val)
{
tcg_gen_movi_tl(cpu_T[1], val);
@@ -3499,13 +3489,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
val = cpu_ldub_code(env, s->pc++);
if (is_xmm) {
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
op1_offset = offsetof(CPUX86State,xmm_t0);
} else {
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
@@ -5379,7 +5369,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
else
val = (int8_t)insn_get(env, s, MO_8);
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_push_T0(s);
break;
case 0x8f: /* pop Ev */
@@ -5508,7 +5498,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
}
val = insn_get(env, s, ot);
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
@@ -5684,7 +5674,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
@@ -5703,7 +5693,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = dflag ? MO_32 : MO_16;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
- gen_op_movl_T0_im(val);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_op_mov_reg_T0(ot, reg);
}
break;
@@ -6507,12 +6497,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
else
ot = dflag ? MO_32 : MO_16;
val = cpu_ldub_code(env, s->pc++);
- gen_op_movl_T0_im(val);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (use_icount)
gen_io_start();
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
gen_op_mov_reg_T1(ot, R_EAX);
if (use_icount) {
@@ -6527,14 +6516,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
else
ot = dflag ? MO_32 : MO_16;
val = cpu_ldub_code(env, s->pc++);
- gen_op_movl_T0_im(val);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
gen_op_mov_TN_reg(ot, 1, R_EAX);
if (use_icount)
gen_io_start();
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_movi_i32(cpu_tmp2_i32, val);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
if (use_icount) {
@@ -6686,7 +6674,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
- gen_op_movl_T0_im(selector);
+ tcg_gen_movi_tl(cpu_T[0], selector);
gen_op_movl_T1_imu(offset);
}
goto do_lcall;
@@ -6712,7 +6700,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
- gen_op_movl_T0_im(selector);
+ tcg_gen_movi_tl(cpu_T[0], selector);
gen_op_movl_T1_imu(offset);
}
goto do_ljmp;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 25/60] target-i386: Remove gen_op_movl_T0_im*
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (23 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 24/60] target-i386: Remove gen_op_movl_T0_im* Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 26/60] target-i386: Remove gen_op_mov*_A0_im Richard Henderson
` (35 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Propagate the definitions into all users. The only time that
gen_op_movl_T1_imu was used, the input was type 'unsigned',
so the replacement works identically.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 30 ++++++++++--------------------
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index d836aee..c89a3e8 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_T1_im(int32_t val)
-{
- tcg_gen_movi_tl(cpu_T[1], val);
-}
-
-static inline void gen_op_movl_T1_imu(uint32_t val)
-{
- tcg_gen_movi_tl(cpu_T[1], val);
-}
-
static inline void gen_op_movl_A0_im(uint32_t val)
{
tcg_gen_movi_tl(cpu_A0, val);
@@ -1934,7 +1924,7 @@ static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
break;
default:
/* currently not optimized */
- gen_op_movl_T1_im(c);
+ tcg_gen_movi_tl(cpu_T[1], c);
gen_shift(s1, op, ot, d, OR_TMP1);
break;
}
@@ -4726,7 +4716,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2: /* OP A, Iv */
val = insn_get(env, s, ot);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
gen_op(s, op, ot, OR_EAX);
break;
}
@@ -4774,7 +4764,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = (int8_t)insn_get(env, s, MO_8);
break;
}
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
gen_op(s, op, ot, opreg);
}
break;
@@ -4812,7 +4802,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(op) {
case 0: /* test */
val = insn_get(env, s, ot);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -5123,7 +5113,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
gen_op_mov_TN_reg(ot, 0, OR_EAX);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -5179,10 +5169,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (b == 0x69) {
val = insn_get(env, s, ot);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
} else if (b == 0x6b) {
val = (int8_t)insn_get(env, s, MO_8);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
} else {
gen_op_mov_TN_reg(ot, 1, reg);
}
@@ -6675,7 +6665,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
selector = insn_get(env, s, MO_16);
tcg_gen_movi_tl(cpu_T[0], selector);
- gen_op_movl_T1_imu(offset);
+ tcg_gen_movi_tl(cpu_T[1], offset);
}
goto do_lcall;
case 0xe9: /* jmp im */
@@ -6701,7 +6691,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
selector = insn_get(env, s, MO_16);
tcg_gen_movi_tl(cpu_T[0], selector);
- gen_op_movl_T1_imu(offset);
+ tcg_gen_movi_tl(cpu_T[1], offset);
}
goto do_ljmp;
case 0xeb: /* jmp Jb */
@@ -6868,7 +6858,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
/* load shift */
val = cpu_ldub_code(env, s->pc++);
- gen_op_movl_T1_im(val);
+ tcg_gen_movi_tl(cpu_T[1], val);
if (op < 4)
goto illegal_op;
op -= 4;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 26/60] target-i386: Remove gen_op_mov*_A0_im
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (24 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 25/60] " Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 27/60] target-i386: Remove gen_movtl_T*_im Richard Henderson
` (34 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Propagate the definitions into all users. In two cases, this allows
us to share code between the 32-bit and 64-bit immediate moves.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c89a3e8..76eeaa1 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,18 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_A0_im(uint32_t val)
-{
- tcg_gen_movi_tl(cpu_A0, val);
-}
-
-#ifdef TARGET_X86_64
-static inline void gen_op_movq_A0_im(int64_t val)
-{
- tcg_gen_movi_tl(cpu_A0, val);
-}
-#endif
-
static inline void gen_movtl_T0_im(target_ulong val)
{
tcg_gen_movi_tl(cpu_T[0], val);
@@ -2046,7 +2034,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
if (rm == 6) {
disp = cpu_lduw_code(env, s->pc);
s->pc += 2;
- gen_op_movl_A0_im(disp);
+ tcg_gen_movi_tl(cpu_A0, disp);
rm = 0; /* avoid SS override */
goto no_rm;
} else {
@@ -5618,7 +5606,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->aflag == 2) {
offset_addr = cpu_ldq_code(env, s->pc);
s->pc += 8;
- gen_op_movq_A0_im(offset_addr);
} else
#endif
{
@@ -5627,8 +5614,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
offset_addr = insn_get(env, s, MO_16);
}
- gen_op_movl_A0_im(offset_addr);
}
+ tcg_gen_movi_tl(cpu_A0, offset_addr);
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 27/60] target-i386: Remove gen_movtl_T*_im
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (25 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 26/60] target-i386: Remove gen_op_mov*_A0_im Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 28/60] target-i386: Remove gen_op_andl_T0_ffff Richard Henderson
` (33 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Propagate the definitions into all users.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 76eeaa1..58bea41 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_movtl_T0_im(target_ulong val)
-{
- tcg_gen_movi_tl(cpu_T[0], val);
-}
-
-static inline void gen_movtl_T1_im(target_ulong val)
-{
- tcg_gen_movi_tl(cpu_T[1], val);
-}
-
static inline void gen_op_andl_T0_ffff(void)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
@@ -5019,7 +5009,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->dflag == 0)
gen_op_andl_T0_ffff();
next_eip = s->pc - s->cs_base;
- gen_movtl_T1_im(next_eip);
+ tcg_gen_movi_tl(cpu_T[1], next_eip);
gen_push_T1(s);
gen_op_jmp_T0();
gen_eob(s);
@@ -5662,7 +5652,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tmp = cpu_ldq_code(env, s->pc);
s->pc += 8;
reg = (b & 7) | REX_B(s);
- gen_movtl_T0_im(tmp);
+ tcg_gen_movi_tl(cpu_T[0], tmp);
gen_op_mov_reg_T0(MO_64, reg);
} else
#endif
@@ -6636,7 +6626,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tval &= 0xffff;
else if(!CODE64(s))
tval &= 0xffffffff;
- gen_movtl_T0_im(next_eip);
+ tcg_gen_movi_tl(cpu_T[0], next_eip);
gen_push_T0(s);
gen_jmp(s, tval);
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 28/60] target-i386: Remove gen_op_andl_T0_ffff
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (26 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 27/60] target-i386: Remove gen_movtl_T*_im Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 29/60] target-i386: Remove gen_op_andl_T0_im Richard Henderson
` (32 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace it with tcg_gen_ext16u_tl. In four places we can combine that
with a previous move into cpu_T[0], and in one place we can infer that
the zero-extension has already happened via the previous load.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 43 ++++++++++++++++++-------------------------
1 file changed, 18 insertions(+), 25 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 58bea41..236d0a7 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_andl_T0_ffff(void)
-{
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
-}
-
static inline void gen_op_andl_T0_im(uint32_t val)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
@@ -5006,8 +5001,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ if (s->dflag == 0) {
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ }
next_eip = s->pc - s->cs_base;
tcg_gen_movi_tl(cpu_T[1], next_eip);
gen_push_T1(s);
@@ -5035,8 +5031,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 4: /* jmp Ev */
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ if (s->dflag == 0) {
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ }
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -6421,8 +6418,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag ? MO_32 : MO_16;
- gen_op_mov_TN_reg(MO_16, 0, R_EDX);
- gen_op_andl_T0_ffff();
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
@@ -6440,8 +6436,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag ? MO_32 : MO_16;
- gen_op_mov_TN_reg(MO_16, 0, R_EDX);
- gen_op_andl_T0_ffff();
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
@@ -6503,8 +6498,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag ? MO_32 : MO_16;
- gen_op_mov_TN_reg(MO_16, 0, R_EDX);
- gen_op_andl_T0_ffff();
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (use_icount)
@@ -6523,8 +6517,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag ? MO_32 : MO_16;
- gen_op_mov_TN_reg(MO_16, 0, R_EDX);
- gen_op_andl_T0_ffff();
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
gen_op_mov_TN_reg(ot, 1, R_EAX);
@@ -6549,16 +6542,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s) && s->dflag)
s->dflag = 2;
gen_stack_update(s, val + (2 << s->dflag));
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ if (s->dflag == 0) {
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ }
gen_op_jmp_T0();
gen_eob(s);
break;
case 0xc3: /* ret */
gen_pop_T0(s);
gen_pop_update(s);
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ if (s->dflag == 0) {
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ }
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -6574,15 +6569,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0);
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
+ gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
gen_op_jmp_T0();
/* pop selector */
gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
gen_stack_update(s, val + (4 << s->dflag));
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 29/60] target-i386: Remove gen_op_andl_T0_im
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (27 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 28/60] target-i386: Remove gen_op_andl_T0_ffff Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 30/60] target-i386: Remove gen_op_movl_T0_T1 Richard Henderson
` (31 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace it with its definition.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 236d0a7..009529e 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_andl_T0_im(uint32_t val)
-{
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
-}
-
static inline void gen_op_movl_T0_T1(void)
{
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
@@ -7362,8 +7357,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
- if (!s->dflag)
- gen_op_andl_T0_im(0xffffff);
+ if (s->dflag == 0) {
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ }
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
break;
case 1:
@@ -7425,8 +7421,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
- if (!s->dflag)
- gen_op_andl_T0_im(0xffffff);
+ if (s->dflag == 0) {
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ }
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
}
break;
@@ -7525,8 +7522,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
- if (!s->dflag)
- gen_op_andl_T0_im(0xffffff);
+ if (s->dflag == 0) {
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ }
if (op == 2) {
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 30/60] target-i386: Remove gen_op_movl_T0_T1
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (28 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 29/60] target-i386: Remove gen_op_andl_T0_im Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 31/60] target-i386: Remove gen_op_andl_A0_ffff Richard Henderson
` (30 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace it with its definition.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 009529e..bb45c2b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_movl_T0_T1(void)
-{
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
-}
-
static inline void gen_op_andl_A0_ffff(void)
{
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
@@ -5045,7 +5040,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_const_i32(s->pc - pc_start));
} else {
gen_op_movl_seg_T0_vm(R_CS);
- gen_op_movl_T0_T1();
+ tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
gen_op_jmp_T0();
}
gen_eob(s);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 31/60] target-i386: Remove gen_op_andl_A0_ffff
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (29 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 30/60] target-i386: Remove gen_op_movl_T0_T1 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 32/60] target-i386: Use TCGMemOp for 'ot' variables Richard Henderson
` (29 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace it with tcg_gen_ext16u_tl, and in two cases merge with a
previous move from cpu_regs.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 33 +++++++++++++--------------------
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index bb45c2b..e075fe3 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s)
}
}
-static inline void gen_op_andl_A0_ffff(void)
-{
- tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
-}
-
#ifdef TARGET_X86_64
#define NB_OP_SIZES 4
@@ -568,8 +563,7 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s)
/* 16 address, always override */
if (override < 0)
override = R_DS;
- gen_op_movl_A0_reg(R_ESI);
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]);
gen_op_addl_A0_seg(s, override);
}
}
@@ -589,8 +583,7 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)
gen_op_movl_A0_reg(R_EDI);
}
} else {
- gen_op_movl_A0_reg(R_EDI);
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]);
gen_op_addl_A0_seg(s, R_ES);
}
}
@@ -2058,7 +2051,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
}
if (disp != 0)
gen_op_addl_A0_im(disp);
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
no_rm:
if (must_add_seg) {
if (override < 0) {
@@ -2391,7 +2384,7 @@ static void gen_push_T0(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
}
} else {
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
@@ -2431,7 +2424,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
}
} else {
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
@@ -2458,7 +2451,7 @@ static void gen_pop_T0(DisasContext *s)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
} else {
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
@@ -2481,7 +2474,7 @@ static void gen_stack_A0(DisasContext *s)
{
gen_op_movl_A0_reg(R_ESP);
if (!s->ss32)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
@@ -2494,7 +2487,7 @@ static void gen_pusha(DisasContext *s)
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-16 << s->dflag);
if (!s->ss32)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
@@ -2512,7 +2505,7 @@ static void gen_popa(DisasContext *s)
int i;
gen_op_movl_A0_reg(R_ESP);
if (!s->ss32)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
if (s->addseg)
@@ -2563,7 +2556,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-opsize);
if (!s->ss32)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
@@ -4423,7 +4416,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
{
gen_op_movl_A0_reg(R_EDI);
if (s->aflag == 0)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
}
gen_add_A0_ds_seg(s);
@@ -5618,7 +5611,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
if (s->aflag == 0)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
else
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
}
@@ -7374,7 +7367,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
gen_op_movl_A0_reg(R_EAX);
if (s->aflag == 0)
- gen_op_andl_A0_ffff();
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
}
gen_add_A0_ds_seg(s);
gen_helper_monitor(cpu_env, cpu_A0);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 32/60] target-i386: Use TCGMemOp for 'ot' variables
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (30 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 31/60] target-i386: Remove gen_op_andl_A0_ffff Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 33/60] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp Richard Henderson
` (28 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
The 'ot' variables (operand type?) hold the log2(byte size) of
the operand being manipulated. This is the same as the MO_SIZE
subset of the TCGMemOp. Indeed, we often pass 'ot' to the
tcg_gen_qemu_ld/st functions.
Changing the type from 'int' makes it easier to see what domain
the variable should be.
This does require adding some default cases to some switch statements,
to avoid the 'unhandled enumeration value' warning that would result
from the change of type.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 120 ++++++++++++++++++++++++++++--------------------
1 file changed, 70 insertions(+), 50 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index e075fe3..31f0d02 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -126,7 +126,7 @@ typedef struct DisasContext {
static void gen_eob(DisasContext *s);
static void gen_jmp(DisasContext *s, target_ulong eip);
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
-static void gen_op(DisasContext *s1, int op, int ot, int d);
+static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d);
/* i386 arith/logic operations */
enum {
@@ -295,7 +295,7 @@ static inline bool byte_reg_is_xH(int reg)
return true;
}
-static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
+static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
{
switch(ot) {
case MO_8:
@@ -308,7 +308,6 @@ static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
case MO_16:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
break;
- default: /* XXX this shouldn't be reached; abort? */
case MO_32:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
@@ -319,26 +318,27 @@ static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
tcg_gen_mov_tl(cpu_regs[reg], t0);
break;
#endif
+ default:
+ tcg_abort();
}
}
-static inline void gen_op_mov_reg_T0(int ot, int reg)
+static inline void gen_op_mov_reg_T0(TCGMemOp ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
-static inline void gen_op_mov_reg_T1(int ot, int reg)
+static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
-static inline void gen_op_mov_reg_A0(int size, int reg)
+static void gen_op_mov_reg_A0(TCGMemOp size, int reg)
{
- switch(size) {
+ switch (size) {
case MO_8:
tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
break;
- default: /* XXX this shouldn't be reached; abort? */
case MO_16:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
@@ -349,10 +349,12 @@ static inline void gen_op_mov_reg_A0(int size, int reg)
tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
break;
#endif
+ default:
+ tcg_abort();
}
}
-static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
+static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
{
if (ot == MO_8 && byte_reg_is_xH(reg)) {
tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
@@ -362,7 +364,7 @@ static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
}
}
-static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
+static inline void gen_op_mov_TN_reg(TCGMemOp ot, int t_index, int reg)
{
gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
}
@@ -588,13 +590,13 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)
}
}
-static inline void gen_op_movl_T0_Dshift(int ot)
+static inline void gen_op_movl_T0_Dshift(TCGMemOp ot)
{
tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
};
-static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
+static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)
{
switch (size) {
case MO_8:
@@ -625,12 +627,12 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
}
}
-static void gen_extu(int ot, TCGv reg)
+static void gen_extu(TCGMemOp ot, TCGv reg)
{
gen_ext_tl(reg, reg, ot, false);
}
-static void gen_exts(int ot, TCGv reg)
+static void gen_exts(TCGMemOp ot, TCGv reg)
{
gen_ext_tl(reg, reg, ot, true);
}
@@ -649,7 +651,7 @@ static inline void gen_op_jz_ecx(int size, int label1)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
}
-static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
+static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
case MO_8:
@@ -661,10 +663,12 @@ static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
case MO_32:
gen_helper_inl(v, n);
break;
+ default:
+ tcg_abort();
}
}
-static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
+static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)
{
switch (ot) {
case MO_8:
@@ -676,10 +680,12 @@ static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
case MO_32:
gen_helper_outl(v, n);
break;
+ default:
+ tcg_abort();
}
}
-static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
+static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
uint32_t svm_flags)
{
int state_saved;
@@ -701,6 +707,8 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
case MO_32:
gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
break;
+ default:
+ tcg_abort();
}
}
if(s->flags & HF_SVMI_MASK) {
@@ -717,7 +725,7 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
}
}
-static inline void gen_movs(DisasContext *s, int ot)
+static inline void gen_movs(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
@@ -911,7 +919,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
default:
{
- int size = (s->cc_op - CC_OP_ADDB) & 3;
+ TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 };
}
@@ -952,7 +960,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 };
default:
{
- int size = (s->cc_op - CC_OP_ADDB) & 3;
+ TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };
}
@@ -963,7 +971,8 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
value 'b'. In the fast case, T0 is guaranted not to be used. */
static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
{
- int inv, jcc_op, size, cond;
+ int inv, jcc_op, cond;
+ TCGMemOp size;
CCPrepare cc;
TCGv t0;
@@ -1143,7 +1152,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
return l2;
}
-static inline void gen_stos(DisasContext *s, int ot)
+static inline void gen_stos(DisasContext *s, TCGMemOp ot)
{
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
gen_string_movl_A0_EDI(s);
@@ -1152,7 +1161,7 @@ static inline void gen_stos(DisasContext *s, int ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
}
-static inline void gen_lods(DisasContext *s, int ot)
+static inline void gen_lods(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
@@ -1161,7 +1170,7 @@ static inline void gen_lods(DisasContext *s, int ot)
gen_op_add_reg_T0(s->aflag, R_ESI);
}
-static inline void gen_scas(DisasContext *s, int ot)
+static inline void gen_scas(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
@@ -1170,7 +1179,7 @@ static inline void gen_scas(DisasContext *s, int ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
}
-static inline void gen_cmps(DisasContext *s, int ot)
+static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
@@ -1181,7 +1190,7 @@ static inline void gen_cmps(DisasContext *s, int ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
}
-static inline void gen_ins(DisasContext *s, int ot)
+static inline void gen_ins(DisasContext *s, TCGMemOp ot)
{
if (use_icount)
gen_io_start();
@@ -1200,7 +1209,7 @@ static inline void gen_ins(DisasContext *s, int ot)
gen_io_end();
}
-static inline void gen_outs(DisasContext *s, int ot)
+static inline void gen_outs(DisasContext *s, TCGMemOp ot)
{
if (use_icount)
gen_io_start();
@@ -1221,7 +1230,7 @@ static inline void gen_outs(DisasContext *s, int ot)
/* same method as Valgrind : we generate jumps to current or next
instruction */
#define GEN_REPZ(op) \
-static inline void gen_repz_ ## op(DisasContext *s, int ot, \
+static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
target_ulong cur_eip, target_ulong next_eip) \
{ \
int l2;\
@@ -1237,7 +1246,7 @@ static inline void gen_repz_ ## op(DisasContext *s, int ot, \
}
#define GEN_REPZ2(op) \
-static inline void gen_repz_ ## op(DisasContext *s, int ot, \
+static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
target_ulong cur_eip, \
target_ulong next_eip, \
int nz) \
@@ -1319,7 +1328,7 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
}
/* if d == OR_TMP0, it means memory operand (address in A0) */
-static void gen_op(DisasContext *s1, int op, int ot, int d)
+static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
{
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
@@ -1385,7 +1394,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
}
/* if d == OR_TMP0, it means memory operand (address in A0) */
-static void gen_inc(DisasContext *s1, int ot, int d, int c)
+static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
{
if (d != OR_TMP0) {
gen_op_mov_TN_reg(ot, 0, d);
@@ -1404,8 +1413,8 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
-static void gen_shift_flags(DisasContext *s, int ot, TCGv result, TCGv shm1,
- TCGv count, bool is_right)
+static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,
+ TCGv shm1, TCGv count, bool is_right)
{
TCGv_i32 z32, s32, oldop;
TCGv z_tl;
@@ -1449,7 +1458,7 @@ static void gen_shift_flags(DisasContext *s, int ot, TCGv result, TCGv shm1,
set_cc_op(s, CC_OP_DYNAMIC);
}
-static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
+static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
int is_right, int is_arith)
{
target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1485,7 +1494,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, cpu_T[1], is_right);
}
-static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
+static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
int is_right, int is_arith)
{
int mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1533,7 +1542,7 @@ static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
tcg_gen_shri_tl(ret, arg1, -arg2);
}
-static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
+static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
{
target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);
TCGv_i32 t0, t1;
@@ -1618,7 +1627,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
set_cc_op(s, CC_OP_DYNAMIC);
}
-static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
+static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
int is_right)
{
int mask = (ot == MO_64 ? 0x3f : 0x1f);
@@ -1696,7 +1705,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
}
/* XXX: add faster immediate = 1 case */
-static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
+static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
int is_right)
{
gen_compute_eflags(s);
@@ -1724,6 +1733,8 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
+ default:
+ tcg_abort();
}
} else {
switch (ot) {
@@ -1741,6 +1752,8 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
break;
#endif
+ default:
+ tcg_abort();
}
}
/* store */
@@ -1748,7 +1761,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
}
/* XXX: add faster immediate case */
-static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
+static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
bool is_right, TCGv count_in)
{
target_ulong mask = (ot == MO_64 ? 63 : 31);
@@ -1829,7 +1842,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
tcg_temp_free(count);
}
-static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
+static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
{
if (s != OR_TMP1)
gen_op_mov_TN_reg(ot, 1, s);
@@ -1859,7 +1872,7 @@ static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
}
}
-static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
+static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c)
{
switch(op) {
case OP_ROL:
@@ -2140,7 +2153,7 @@ static void gen_add_A0_ds_seg(DisasContext *s)
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
OR_TMP0 */
static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
- int ot, int reg, int is_store)
+ TCGMemOp ot, int reg, int is_store)
{
int mod, rm;
@@ -2170,11 +2183,11 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
}
}
-static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
+static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)
{
uint32_t ret;
- switch(ot) {
+ switch (ot) {
case MO_8:
ret = cpu_ldub_code(env, s->pc);
s->pc++;
@@ -2183,16 +2196,20 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
ret = cpu_lduw_code(env, s->pc);
s->pc += 2;
break;
- default:
case MO_32:
+#ifdef TARGET_X86_64
+ case MO_64:
+#endif
ret = cpu_ldl_code(env, s->pc);
s->pc += 4;
break;
+ default:
+ tcg_abort();
}
return ret;
}
-static inline int insn_const_size(unsigned int ot)
+static inline int insn_const_size(TCGMemOp ot)
{
if (ot <= MO_32)
return 1 << ot;
@@ -2250,7 +2267,7 @@ static inline void gen_jcc(DisasContext *s, int b,
}
}
-static void gen_cmovcc1(CPUX86State *env, DisasContext *s, int ot, int b,
+static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
int modrm, int reg)
{
CCPrepare cc;
@@ -2523,7 +2540,8 @@ static void gen_popa(DisasContext *s)
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
- int ot, opsize;
+ TCGMemOp ot;
+ int opsize;
level &= 0x1f;
#ifdef TARGET_X86_64
@@ -3035,12 +3053,13 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = {
static void gen_sse(CPUX86State *env, DisasContext *s, int b,
target_ulong pc_start, int rex_r)
{
- int b1, op1_offset, op2_offset, is_xmm, val, ot;
+ int b1, op1_offset, op2_offset, is_xmm, val;
int modrm, mod, rm, reg;
SSEFunc_0_epp sse_fn_epp;
SSEFunc_0_eppi sse_fn_eppi;
SSEFunc_0_ppi sse_fn_ppi;
SSEFunc_0_eppt sse_fn_eppt;
+ TCGMemOp ot;
b &= 0xff;
if (s->prefix & PREFIX_DATA)
@@ -4444,7 +4463,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong pc_start)
{
int b, prefixes, aflag, dflag;
- int shift, ot;
+ int shift;
+ TCGMemOp ot;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 33/60] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (31 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 32/60] target-i386: Use TCGMemOp for 'ot' variables Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 34/60] target-i386: Change gen_op_j*z_ecx " Richard Henderson
` (27 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
These functions used the aflags/dflags domain, which is log2-1
of the byte size. Confusingly, they used enumeration values
from the log2 domain.
Change the domain of the parameter and update all callers.
Since we're now in a common domain, defer the deposit/extend/mov
decision to gen_op_mov_reg_v.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 76 ++++++++++++++-----------------------------------
1 file changed, 22 insertions(+), 54 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 31f0d02..087f0a2 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -409,48 +409,16 @@ static inline void gen_op_jmp_T0(void)
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
}
-static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
+static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val)
{
- switch(size) {
- case MO_8:
- tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
- tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
- break;
- case MO_16:
- tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
- /* For x86_64, this sets the higher half of register to zero.
- For i386, this is equivalent to a nop. */
- tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
- tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
- break;
-#ifdef TARGET_X86_64
- case MO_32:
- tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
- break;
-#endif
- }
+ tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
+ gen_op_mov_reg_v(size, reg, cpu_tmp0);
}
-static inline void gen_op_add_reg_T0(int size, int reg)
+static inline void gen_op_add_reg_T0(TCGMemOp size, int reg)
{
- switch(size) {
- case MO_8:
- tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
- tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
- break;
- case MO_16:
- tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
- /* For x86_64, this sets the higher half of register to zero.
- For i386, this is equivalent to a nop. */
- tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
- tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
- break;
-#ifdef TARGET_X86_64
- case MO_32:
- tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
- break;
-#endif
- }
+ tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
+ gen_op_mov_reg_v(size, reg, cpu_tmp0);
}
static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
@@ -732,8 +700,8 @@ static inline void gen_movs(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_ESI);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_ESI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
}
static void gen_op_update1_cc(void)
@@ -1158,7 +1126,7 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
}
static inline void gen_lods(DisasContext *s, TCGMemOp ot)
@@ -1167,7 +1135,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_op_add_reg_T0(s->aflag + 1, R_ESI);
}
static inline void gen_scas(DisasContext *s, TCGMemOp ot)
@@ -1176,7 +1144,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot)
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
}
static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
@@ -1186,8 +1154,8 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_ESI);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_ESI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
}
static inline void gen_ins(DisasContext *s, TCGMemOp ot)
@@ -1204,7 +1172,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_op_add_reg_T0(s->aflag + 1, R_EDI);
if (use_icount)
gen_io_end();
}
@@ -1222,7 +1190,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_op_add_reg_T0(s->aflag + 1, R_ESI);
if (use_icount)
gen_io_end();
}
@@ -1237,7 +1205,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
- gen_op_add_reg_im(s->aflag, R_ECX, -1); \
+ gen_op_add_reg_im(s->aflag + 1, R_ECX, -1); \
/* a loop would cause two single step exceptions if ECX = 1 \
before rep string_insn */ \
if (!s->jmp_opt) \
@@ -1255,7 +1223,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
- gen_op_add_reg_im(s->aflag, R_ECX, -1); \
+ gen_op_add_reg_im(s->aflag + 1, R_ECX, -1); \
gen_update_cc_op(s); \
gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
if (!s->jmp_opt) \
@@ -2363,13 +2331,13 @@ static inline void gen_stack_update(DisasContext *s, int addend)
{
#ifdef TARGET_X86_64
if (CODE64(s)) {
- gen_op_add_reg_im(2, R_ESP, addend);
+ gen_op_add_reg_im(MO_64, R_ESP, addend);
} else
#endif
if (s->ss32) {
- gen_op_add_reg_im(1, R_ESP, addend);
+ gen_op_add_reg_im(MO_32, R_ESP, addend);
} else {
- gen_op_add_reg_im(0, R_ESP, addend);
+ gen_op_add_reg_im(MO_16, R_ESP, addend);
}
}
@@ -7164,12 +7132,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(b) {
case 0: /* loopnz */
case 1: /* loopz */
- gen_op_add_reg_im(s->aflag, R_ECX, -1);
+ gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
gen_op_jz_ecx(s->aflag, l3);
gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
break;
case 2: /* loop */
- gen_op_add_reg_im(s->aflag, R_ECX, -1);
+ gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
gen_op_jnz_ecx(s->aflag, l1);
break;
default:
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 34/60] target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (32 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 33/60] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 35/60] target-i386: Change aflag " Richard Henderson
` (26 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Change the domain of the parameter and update all callers.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 087f0a2..1fdd56b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -605,17 +605,17 @@ static void gen_exts(TCGMemOp ot, TCGv reg)
gen_ext_tl(reg, reg, ot, true);
}
-static inline void gen_op_jnz_ecx(int size, int label1)
+static inline void gen_op_jnz_ecx(TCGMemOp size, int label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
- gen_extu(size + 1, cpu_tmp0);
+ gen_extu(size, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
}
-static inline void gen_op_jz_ecx(int size, int label1)
+static inline void gen_op_jz_ecx(TCGMemOp size, int label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
- gen_extu(size + 1, cpu_tmp0);
+ gen_extu(size, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
}
@@ -1113,7 +1113,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
l1 = gen_new_label();
l2 = gen_new_label();
- gen_op_jnz_ecx(s->aflag, l1);
+ gen_op_jnz_ecx(s->aflag + 1, l1);
gen_set_label(l2);
gen_jmp_tb(s, next_eip, 1);
gen_set_label(l1);
@@ -1209,7 +1209,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
/* a loop would cause two single step exceptions if ECX = 1 \
before rep string_insn */ \
if (!s->jmp_opt) \
- gen_op_jz_ecx(s->aflag, l2); \
+ gen_op_jz_ecx(s->aflag + 1, l2); \
gen_jmp(s, cur_eip); \
}
@@ -1227,7 +1227,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
if (!s->jmp_opt) \
- gen_op_jz_ecx(s->aflag, l2); \
+ gen_op_jz_ecx(s->aflag + 1, l2); \
gen_jmp(s, cur_eip); \
}
@@ -7133,16 +7133,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0: /* loopnz */
case 1: /* loopz */
gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
- gen_op_jz_ecx(s->aflag, l3);
+ gen_op_jz_ecx(s->aflag + 1, l3);
gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
break;
case 2: /* loop */
gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
- gen_op_jnz_ecx(s->aflag, l1);
+ gen_op_jnz_ecx(s->aflag + 1, l1);
break;
default:
case 3: /* jcxz */
- gen_op_jz_ecx(s->aflag, l1);
+ gen_op_jz_ecx(s->aflag + 1, l1);
break;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 35/60] target-i386: Change aflag to TCGMemOp
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (33 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 34/60] target-i386: Change gen_op_j*z_ecx " Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 36/60] target-i386: Change gen_op_mov_reg_A0 size parameter " Richard Henderson
` (25 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Changing the domain to TCGMemOp makes it easier to interoperate
with other portions of the rest of the translator.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 177 +++++++++++++++++++++++-------------------------
1 file changed, 86 insertions(+), 91 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 1fdd56b..8a9e7b7 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -85,7 +85,8 @@ typedef struct DisasContext {
/* current insn context */
int override; /* -1 if no override */
int prefix;
- int aflag, dflag;
+ TCGMemOp aflag;
+ int dflag;
target_ulong pc; /* pc = eip + cs_base */
int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
static state change (stop translation) */
@@ -509,17 +510,18 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s)
int override;
override = s->override;
+ switch (s->aflag) {
#ifdef TARGET_X86_64
- if (s->aflag == 2) {
+ case MO_64:
if (override >= 0) {
gen_op_movq_A0_seg(override);
gen_op_addq_A0_reg_sN(0, R_ESI);
} else {
gen_op_movq_A0_reg(R_ESI);
}
- } else
+ break;
#endif
- if (s->aflag) {
+ case MO_32:
/* 32 bit address */
if (s->addseg && override < 0)
override = R_DS;
@@ -529,32 +531,41 @@ static inline void gen_string_movl_A0_ESI(DisasContext *s)
} else {
gen_op_movl_A0_reg(R_ESI);
}
- } else {
+ break;
+ case MO_16:
/* 16 address, always override */
if (override < 0)
override = R_DS;
tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]);
gen_op_addl_A0_seg(s, override);
+ break;
+ default:
+ tcg_abort();
}
}
static inline void gen_string_movl_A0_EDI(DisasContext *s)
{
+ switch (s->aflag) {
#ifdef TARGET_X86_64
- if (s->aflag == 2) {
+ case MO_64:
gen_op_movq_A0_reg(R_EDI);
- } else
+ break;
#endif
- if (s->aflag) {
+ case MO_32:
if (s->addseg) {
gen_op_movl_A0_seg(R_ES);
gen_op_addl_A0_reg_sN(0, R_EDI);
} else {
gen_op_movl_A0_reg(R_EDI);
}
- } else {
+ break;
+ case MO_16:
tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]);
gen_op_addl_A0_seg(s, R_ES);
+ break;
+ default:
+ tcg_abort();
}
}
@@ -700,8 +711,8 @@ static inline void gen_movs(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_ESI);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
}
static void gen_op_update1_cc(void)
@@ -1113,7 +1124,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
l1 = gen_new_label();
l2 = gen_new_label();
- gen_op_jnz_ecx(s->aflag + 1, l1);
+ gen_op_jnz_ecx(s->aflag, l1);
gen_set_label(l2);
gen_jmp_tb(s, next_eip, 1);
gen_set_label(l1);
@@ -1126,7 +1137,7 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_lods(DisasContext *s, TCGMemOp ot)
@@ -1135,7 +1146,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_ESI);
+ gen_op_add_reg_T0(s->aflag, R_ESI);
}
static inline void gen_scas(DisasContext *s, TCGMemOp ot)
@@ -1144,7 +1155,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot)
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
@@ -1154,8 +1165,8 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_ESI);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_ins(DisasContext *s, TCGMemOp ot)
@@ -1172,7 +1183,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_EDI);
+ gen_op_add_reg_T0(s->aflag, R_EDI);
if (use_icount)
gen_io_end();
}
@@ -1190,7 +1201,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_op_movl_T0_Dshift(ot);
- gen_op_add_reg_T0(s->aflag + 1, R_ESI);
+ gen_op_add_reg_T0(s->aflag, R_ESI);
if (use_icount)
gen_io_end();
}
@@ -1205,11 +1216,11 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
- gen_op_add_reg_im(s->aflag + 1, R_ECX, -1); \
+ gen_op_add_reg_im(s->aflag, R_ECX, -1); \
/* a loop would cause two single step exceptions if ECX = 1 \
before rep string_insn */ \
if (!s->jmp_opt) \
- gen_op_jz_ecx(s->aflag + 1, l2); \
+ gen_op_jz_ecx(s->aflag, l2); \
gen_jmp(s, cur_eip); \
}
@@ -1223,11 +1234,11 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
gen_update_cc_op(s); \
l2 = gen_jz_ecx_string(s, next_eip); \
gen_ ## op(s, ot); \
- gen_op_add_reg_im(s->aflag + 1, R_ECX, -1); \
+ gen_op_add_reg_im(s->aflag, R_ECX, -1); \
gen_update_cc_op(s); \
gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
if (!s->jmp_opt) \
- gen_op_jz_ecx(s->aflag + 1, l2); \
+ gen_op_jz_ecx(s->aflag, l2); \
gen_jmp(s, cur_eip); \
}
@@ -1884,7 +1895,9 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
mod = (modrm >> 6) & 3;
rm = modrm & 7;
- if (s->aflag) {
+ switch (s->aflag) {
+ case MO_64:
+ case MO_32:
havesib = 0;
base = rm;
index = -1;
@@ -1964,7 +1977,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
tcg_gen_ld_tl(cpu_tmp0, cpu_env,
offsetof(CPUX86State, segs[override].base));
if (CODE64(s)) {
- if (s->aflag != 2) {
+ if (s->aflag == MO_32) {
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
@@ -1974,10 +1987,12 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
}
- if (s->aflag != 2) {
+ if (s->aflag == MO_32) {
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
- } else {
+ break;
+
+ case MO_16:
switch (mod) {
case 0:
if (rm == 6) {
@@ -2043,6 +2058,10 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
}
gen_op_addl_A0_seg(s, override);
}
+ break;
+
+ default:
+ tcg_abort();
}
}
@@ -2055,8 +2074,9 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
return;
rm = modrm & 7;
- if (s->aflag) {
-
+ switch (s->aflag) {
+ case MO_64:
+ case MO_32:
base = rm;
if (base == 4) {
@@ -2078,7 +2098,9 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
s->pc += 4;
break;
}
- } else {
+ break;
+
+ case MO_16:
switch (mod) {
case 0:
if (rm == 6) {
@@ -2093,6 +2115,10 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
s->pc += 2;
break;
}
+ break;
+
+ default:
+ tcg_abort();
}
}
@@ -4395,16 +4421,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* maskmov : we must prepare A0 */
if (mod != 3)
goto illegal_op;
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_movq_A0_reg(R_EDI);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_EDI);
- if (s->aflag == 0)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- }
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EDI]);
+ gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
@@ -4430,9 +4448,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong pc_start)
{
- int b, prefixes, aflag, dflag;
+ int b, prefixes, dflag;
int shift;
- TCGMemOp ot;
+ TCGMemOp ot, aflag;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
@@ -4570,7 +4588,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
over 0x66 if both are present. */
dflag = (rex_w > 0 ? 2 : prefixes & PREFIX_DATA ? 0 : 1);
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
- aflag = (prefixes & PREFIX_ADR ? 1 : 2);
+ aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
} else {
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
dflag = s->code32;
@@ -4578,9 +4596,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
dflag ^= 1;
}
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
- aflag = s->code32;
- if (prefixes & PREFIX_ADR) {
- aflag ^= 1;
+ if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {
+ aflag = MO_32;
+ } else {
+ aflag = MO_16;
}
}
@@ -5560,18 +5579,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_8;
else
ot = dflag + MO_16;
+ switch (s->aflag) {
#ifdef TARGET_X86_64
- if (s->aflag == 2) {
+ case MO_64:
offset_addr = cpu_ldq_code(env, s->pc);
s->pc += 8;
- } else
+ break;
#endif
- {
- if (s->aflag) {
- offset_addr = insn_get(env, s, MO_32);
- } else {
- offset_addr = insn_get(env, s, MO_16);
- }
+ default:
+ offset_addr = insn_get(env, s, s->aflag);
+ break;
}
tcg_gen_movi_tl(cpu_A0, offset_addr);
gen_add_A0_ds_seg(s);
@@ -5585,24 +5602,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
break;
case 0xd7: /* xlat */
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_movq_A0_reg(R_EBX);
- gen_op_mov_TN_reg(MO_64, 0, R_EAX);
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_EBX);
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
- if (s->aflag == 0)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- else
- tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
- }
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EBX]);
+ tcg_gen_ext8u_tl(cpu_T[0], cpu_regs[R_EAX]);
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
+ gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
gen_op_mov_reg_T0(MO_8, R_EAX);
@@ -7132,17 +7135,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(b) {
case 0: /* loopnz */
case 1: /* loopz */
- gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
- gen_op_jz_ecx(s->aflag + 1, l3);
+ gen_op_add_reg_im(s->aflag, R_ECX, -1);
+ gen_op_jz_ecx(s->aflag, l3);
gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
break;
case 2: /* loop */
- gen_op_add_reg_im(s->aflag + 1, R_ECX, -1);
- gen_op_jnz_ecx(s->aflag + 1, l1);
+ gen_op_add_reg_im(s->aflag, R_ECX, -1);
+ gen_op_jnz_ecx(s->aflag, l1);
break;
default:
case 3: /* jcxz */
- gen_op_jz_ecx(s->aflag + 1, l1);
+ gen_op_jz_ecx(s->aflag, l1);
break;
}
@@ -7347,16 +7350,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
-#ifdef TARGET_X86_64
- if (s->aflag == 2) {
- gen_op_movq_A0_reg(R_EAX);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_EAX);
- if (s->aflag == 0)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- }
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EAX]);
+ gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
gen_helper_monitor(cpu_env, cpu_A0);
break;
@@ -7416,7 +7411,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
} else {
- gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag),
+ gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1),
tcg_const_i32(s->pc - pc_start));
tcg_gen_exit_tb(0);
s->is_jmp = DISAS_TB_JUMP;
@@ -7434,7 +7429,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
} else {
- gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag));
+ gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1));
}
break;
case 3: /* VMSAVE */
@@ -7444,7 +7439,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
} else {
- gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag));
+ gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1));
}
break;
case 4: /* STGI */
@@ -7483,7 +7478,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
} else {
- gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag));
+ gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag - 1));
}
break;
default:
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 36/60] target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (34 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 35/60] target-i386: Change aflag " Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 37/60] target-i386: Change dflag " Richard Henderson
` (24 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Change the domain of the parameter and update all callers.
Which lets us defer completely to gen_op_mov_reg_v.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 32 ++++++++------------------------
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8a9e7b7..b75a9b6 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -334,25 +334,9 @@ static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
-static void gen_op_mov_reg_A0(TCGMemOp size, int reg)
+static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg)
{
- switch (size) {
- case MO_8:
- tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
- break;
- case MO_16:
- /* For x86_64, this sets the higher half of register to zero.
- For i386, this is equivalent to a mov. */
- tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
- break;
-#ifdef TARGET_X86_64
- case MO_32:
- tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
- break;
-#endif
- default:
- tcg_abort();
- }
+ gen_op_mov_reg_v(size, reg, cpu_A0);
}
static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
@@ -2380,7 +2364,7 @@ static void gen_push_T0(DisasContext *s)
gen_op_addq_A0_im(-2);
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
}
- gen_op_mov_reg_A0(2, R_ESP);
+ gen_op_mov_reg_A0(MO_64, R_ESP);
} else
#endif
{
@@ -2401,9 +2385,9 @@ static void gen_push_T0(DisasContext *s)
}
gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(1, R_ESP);
+ gen_op_mov_reg_A0(MO_32, R_ESP);
else
- gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
+ gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
}
@@ -2421,7 +2405,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_addq_A0_im(-2);
gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0);
}
- gen_op_mov_reg_A0(2, R_ESP);
+ gen_op_mov_reg_A0(MO_64, R_ESP);
} else
#endif
{
@@ -2441,7 +2425,7 @@ static void gen_push_T1(DisasContext *s)
gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(1, R_ESP);
+ gen_op_mov_reg_A0(MO_32, R_ESP);
else
gen_stack_update(s, (-2) << s->dflag);
}
@@ -5565,7 +5549,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->addseg = 0;
gen_lea_modrm(env, s, modrm);
s->addseg = val;
- gen_op_mov_reg_A0(ot - MO_16, reg);
+ gen_op_mov_reg_A0(ot, reg);
break;
case 0xa0: /* mov EAX, Ov */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 37/60] target-i386: Change dflag to TCGMemOp
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (35 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 36/60] target-i386: Change gen_op_mov_reg_A0 size parameter " Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 38/60] target-i386: Tidy addr16 code in gen_lea_modrm Richard Henderson
` (23 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Changing the domain to TCGMemOp makes it easier to interoperate
with other portions of the rest of the translator.
We now only have one domain for size operands inside the translator,
which makes things less confusing all the way around. There are
still a number of helpers that continue to use the log2-1 domain.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 498 +++++++++++++++++++++---------------------------
1 file changed, 214 insertions(+), 284 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index b75a9b6..a12f159 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -86,7 +86,7 @@ typedef struct DisasContext {
int override; /* -1 if no override */
int prefix;
TCGMemOp aflag;
- int dflag;
+ TCGMemOp dflag;
target_ulong pc; /* pc = eip + cs_base */
int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
static state change (stop translation) */
@@ -296,6 +296,40 @@ static inline bool byte_reg_is_xH(int reg)
return true;
}
+/* Select the size of a push/pop operation. */
+static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
+{
+ if (CODE64(s)) {
+ return ot == MO_16 ? MO_16 : MO_64;
+ } else {
+ return ot;
+ }
+}
+
+/* Select only size 64 else 32. Used for SSE operand sizes. */
+static inline TCGMemOp mo_64_32(TCGMemOp ot)
+{
+#ifdef TARGET_X86_64
+ return ot == MO_64 ? MO_64 : MO_32;
+#else
+ return MO_32;
+#endif
+}
+
+/* Select size 8 if lsb of B is clear, else OT. Used for decoding
+ byte vs word opcodes. */
+static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)
+{
+ return b & 1 ? ot : MO_8;
+}
+
+/* Select size 8 if lsb of B is clear, else OT capped at 32.
+ Used for decoding operand size of port opcodes. */
+static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)
+{
+ return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;
+}
+
static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
{
switch(ot) {
@@ -2357,7 +2391,7 @@ static void gen_push_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- if (s->dflag) {
+ if (s->dflag != MO_16) {
gen_op_addq_A0_im(-8);
gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0);
} else {
@@ -2369,10 +2403,7 @@ static void gen_push_T0(DisasContext *s)
#endif
{
gen_op_movl_A0_reg(R_ESP);
- if (!s->dflag)
- gen_op_addl_A0_im(-2);
- else
- gen_op_addl_A0_im(-4);
+ gen_op_addl_A0_im(-1 << s->dflag);
if (s->ss32) {
if (s->addseg) {
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2383,7 +2414,7 @@ static void gen_push_T0(DisasContext *s)
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(MO_32, R_ESP);
else
@@ -2398,7 +2429,7 @@ static void gen_push_T1(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- if (s->dflag) {
+ if (s->dflag != MO_16) {
gen_op_addq_A0_im(-8);
gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
} else {
@@ -2410,10 +2441,7 @@ static void gen_push_T1(DisasContext *s)
#endif
{
gen_op_movl_A0_reg(R_ESP);
- if (!s->dflag)
- gen_op_addl_A0_im(-2);
- else
- gen_op_addl_A0_im(-4);
+ gen_op_addl_A0_im(-1 << s->dflag);
if (s->ss32) {
if (s->addseg) {
gen_op_addl_A0_seg(s, R_SS);
@@ -2422,12 +2450,12 @@ static void gen_push_T1(DisasContext *s)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
+ gen_op_st_v(s, s->dflag, cpu_T[1], cpu_A0);
if (s->ss32 && !s->addseg)
gen_op_mov_reg_A0(MO_32, R_ESP);
else
- gen_stack_update(s, (-2) << s->dflag);
+ gen_stack_update(s, -1 << s->dflag);
}
}
@@ -2437,7 +2465,7 @@ static void gen_pop_T0(DisasContext *s)
#ifdef TARGET_X86_64
if (CODE64(s)) {
gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_v(s, s->dflag ? MO_64 : MO_16, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, mo_pushpop(s, s->dflag), cpu_T[0], cpu_A0);
} else
#endif
{
@@ -2449,20 +2477,13 @@ static void gen_pop_T0(DisasContext *s)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
}
- gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
}
}
static void gen_pop_update(DisasContext *s)
{
-#ifdef TARGET_X86_64
- if (CODE64(s) && s->dflag) {
- gen_stack_update(s, 8);
- } else
-#endif
- {
- gen_stack_update(s, 2 << s->dflag);
- }
+ gen_stack_update(s, 1 << mo_pushpop(s, s->dflag));
}
static void gen_stack_A0(DisasContext *s)
@@ -2480,7 +2501,7 @@ static void gen_pusha(DisasContext *s)
{
int i;
gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-16 << s->dflag);
+ gen_op_addl_A0_im(-8 << s->dflag);
if (!s->ss32)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2488,8 +2509,8 @@ static void gen_pusha(DisasContext *s)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg(MO_32, 0, 7 - i);
- gen_op_st_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
- gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
+ gen_op_addl_A0_im(1 << s->dflag);
}
gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
@@ -2502,31 +2523,28 @@ static void gen_popa(DisasContext *s)
if (!s->ss32)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
+ tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 8 << s->dflag);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i);
+ gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
+ gen_op_mov_reg_T0(s->dflag, 7 - i);
}
- gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_addl_A0_im(1 << s->dflag);
}
gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
- TCGMemOp ot;
- int opsize;
+ TCGMemOp ot = mo_pushpop(s, s->dflag);
+ int opsize = 1 << ot;
level &= 0x1f;
#ifdef TARGET_X86_64
if (CODE64(s)) {
- ot = s->dflag ? MO_64 : MO_16;
- opsize = 1 << ot;
-
gen_op_movl_A0_reg(R_ESP);
gen_op_addq_A0_im(-opsize);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
@@ -2546,9 +2564,6 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
} else
#endif
{
- ot = s->dflag + MO_16;
- opsize = 2 << s->dflag;
-
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-opsize);
if (!s->ss32)
@@ -2562,7 +2577,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
if (level) {
/* XXX: must save state */
gen_helper_enter_level(cpu_env, tcg_const_i32(level),
- tcg_const_i32(s->dflag),
+ tcg_const_i32(s->dflag - 1),
cpu_T[1]);
}
gen_op_mov_reg_T1(ot, R_EBP);
@@ -3136,7 +3151,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x6e: /* movd mm, ea */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
} else
@@ -3151,7 +3166,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x16e: /* movd xmm, ea */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
@@ -3316,7 +3331,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x7e: /* movd ea, mm */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
@@ -3330,7 +3345,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x17e: /* movd ea, xmm */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
@@ -3500,7 +3515,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x22a: /* cvtsi2ss */
case 0x32a: /* cvtsi2sd */
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
@@ -3552,7 +3567,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x32c: /* cvttsd2si */
case 0x22d: /* cvtss2si */
case 0x32d: /* cvtsd2si */
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
if ((b >> 8) & 1) {
@@ -3602,7 +3617,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x1c5:
if (mod != 3)
goto illegal_op;
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
@@ -3755,7 +3770,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
if ((b & 0xff) == 0xf0) {
ot = MO_8;
- } else if (s->dflag != 2) {
+ } else if (s->dflag != MO_64) {
ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
ot = MO_64;
@@ -3766,7 +3781,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
cpu_T[0], tcg_const_i32(8 << ot));
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_op_mov_reg_T0(ot, reg);
break;
@@ -3784,7 +3799,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) {
goto illegal_op;
}
- if (s->dflag != 2) {
+ if (s->dflag != MO_64) {
ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
ot = MO_64;
@@ -3807,7 +3822,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
gen_op_mov_reg_T0(ot, reg);
@@ -3821,7 +3836,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
{
TCGv bound, zero;
@@ -3861,7 +3876,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]);
{
@@ -3888,7 +3903,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (ot) {
default:
@@ -3914,11 +3929,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
- if (s->dflag == 2) {
+ if (ot == MO_64) {
tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
} else {
tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
@@ -3932,11 +3947,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
- if (s->dflag == 2) {
+ if (ot == MO_64) {
tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
} else {
tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
@@ -3952,7 +3967,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
TCGv carry_in, carry_out, zero;
int end_op;
- ot = (s->dflag == 2 ? MO_64 : MO_32);
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Re-use the carry-out from a previous round. */
@@ -4031,7 +4046,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = (s->dflag == 2 ? MO_64 : MO_32);
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (ot == MO_64) {
tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
@@ -4063,7 +4078,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (reg & 7) {
@@ -4120,7 +4135,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
if (sse_fn_eppi == SSE_SPECIAL) {
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
rm = (modrm & 7) | REX_B(s);
if (mod != 3)
gen_lea_modrm(env, s, modrm);
@@ -4278,7 +4293,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
set_cc_op(s, CC_OP_EFLAGS);
- if (s->dflag == 2)
+ if (s->dflag == MO_64)
/* The helper must use entire 64-bit gp registers */
val |= 1 << 8;
}
@@ -4301,7 +4316,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
b = cpu_ldub_code(env, s->pc++);
if (ot == MO_64) {
@@ -4432,9 +4447,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong pc_start)
{
- int b, prefixes, dflag;
+ int b, prefixes;
int shift;
- TCGMemOp ot, aflag;
+ TCGMemOp ot, aflag, dflag;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
@@ -4570,14 +4585,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* In 64-bit mode, the default data size is 32-bit. Select 64-bit
data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
over 0x66 if both are present. */
- dflag = (rex_w > 0 ? 2 : prefixes & PREFIX_DATA ? 0 : 1);
+ dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
} else {
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
- dflag = s->code32;
- if (prefixes & PREFIX_DATA) {
- dflag ^= 1;
+ if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {
+ dflag = MO_32;
+ } else {
+ dflag = MO_16;
}
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {
@@ -4619,10 +4635,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = (b >> 3) & 7;
f = (b >> 1) & 3;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
switch(f) {
case 0: /* OP Ev, Gv */
@@ -4679,10 +4692,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
int val;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4719,19 +4729,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* inc, dec, and other misc arith */
case 0x40 ... 0x47: /* inc Gv */
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), 1);
break;
case 0x48 ... 0x4f: /* dec Gv */
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), -1);
break;
case 0xf6: /* GRP3 */
case 0xf7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4927,10 +4934,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xfe: /* GRP4 */
case 0xff: /* GRP5 */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
@@ -4944,10 +4948,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* operand size for jumps is 64 bit */
ot = MO_64;
} else if (op == 3 || op == 5) {
- ot = dflag ? MO_32 + (rex_w == 1) : MO_16;
+ ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16;
} else if (op == 6) {
/* default push size is 64 bit */
- ot = dflag ? MO_64 : MO_16;
+ ot = mo_pushpop(s, dflag);
}
}
if (mod != 3) {
@@ -4975,7 +4979,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
next_eip = s->pc - s->cs_base;
@@ -4994,18 +4998,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
- tcg_const_i32(dflag),
+ tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - pc_start));
} else {
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
- tcg_const_i32(dflag),
+ tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
}
gen_eob(s);
break;
case 4: /* jmp Ev */
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -5039,10 +5043,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x84: /* test Ev, Gv */
case 0x85:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5055,10 +5056,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa8: /* test eAX, Iv */
case 0xa9:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
gen_op_mov_TN_reg(ot, 0, OR_EAX);
@@ -5068,47 +5066,57 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x98: /* CWDE/CBW */
+ switch (dflag) {
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ case MO_64:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_64, R_EAX);
- } else
+ break;
#endif
- if (dflag == 1) {
+ case MO_32:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_32, R_EAX);
- } else {
+ break;
+ case MO_16:
gen_op_mov_TN_reg(MO_8, 0, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_16, R_EAX);
+ break;
+ default:
+ tcg_abort();
}
break;
case 0x99: /* CDQ/CWD */
+ switch (dflag) {
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ case MO_64:
gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
gen_op_mov_reg_T0(MO_64, R_EDX);
- } else
+ break;
#endif
- if (dflag == 1) {
+ case MO_32:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
gen_op_mov_reg_T0(MO_32, R_EDX);
- } else {
+ break;
+ case MO_16:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
gen_op_mov_reg_T0(MO_16, R_EDX);
+ break;
+ default:
+ tcg_abort();
}
break;
case 0x1af: /* imul Gv, Ev */
case 0x69: /* imul Gv, Ev, I */
case 0x6b:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
if (b == 0x69)
@@ -5160,10 +5168,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1c0:
case 0x1c1: /* xadd Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5191,10 +5196,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
int label1, label2;
TCGv t0, t1, t2, a0;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5250,7 +5252,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if ((mod == 3) || ((modrm & 0x38) != 0x8))
goto illegal_op;
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
goto illegal_op;
gen_jmp_im(pc_start - s->cs_base);
@@ -5277,11 +5279,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_T0(s);
break;
case 0x58 ... 0x5f: /* pop */
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s);
@@ -5299,11 +5297,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x68: /* push Iv */
case 0x6a:
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
if (b == 0x68)
val = insn_get(env, s, ot);
else
@@ -5312,11 +5306,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_T0(s);
break;
case 0x8f: /* pop Ev */
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
gen_pop_T0(s);
@@ -5355,11 +5345,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_reg_T0(MO_16, R_ESP);
}
gen_pop_T0(s);
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
gen_op_mov_reg_T0(ot, R_EBP);
gen_pop_update(s);
break;
@@ -5414,10 +5400,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* mov */
case 0x88:
case 0x89: /* mov Gv, Ev */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5426,10 +5409,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xc6:
case 0xc7: /* mov Ev, Iv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod != 3) {
@@ -5446,10 +5426,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x8a:
case 0x8b: /* mov Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = MO_16 + dflag;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -5483,10 +5460,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (reg >= 6)
goto illegal_op;
gen_op_movl_T0_seg(reg);
- if (mod == 3)
- ot = MO_16 + dflag;
- else
- ot = MO_16;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
@@ -5499,7 +5473,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGMemOp s_ot;
/* d_ot is the size of destination */
- d_ot = dflag + MO_16;
+ d_ot = dflag;
/* ot is the size of source */
ot = (b & 1) + MO_8;
/* s_ot is the sign+size of source */
@@ -5537,7 +5511,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x8d: /* lea */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -5559,10 +5533,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
target_ulong offset_addr;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
switch (s->aflag) {
#ifdef TARGET_X86_64
case MO_64:
@@ -5601,7 +5572,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
uint64_t tmp;
/* 64 bit case */
tmp = cpu_ldq_code(env, s->pc);
@@ -5612,7 +5583,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else
#endif
{
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], val);
@@ -5622,16 +5593,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x91 ... 0x97: /* xchg R, EAX */
do_xchg_reg_eax:
- ot = dflag + MO_16;
+ ot = dflag;
reg = (b & 7) | REX_B(s);
rm = R_EAX;
goto do_xchg_reg;
case 0x86:
case 0x87: /* xchg Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5672,7 +5640,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1b5: /* lgs Gv */
op = R_GS;
do_lxx:
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -5700,11 +5668,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
shift = 2;
grp2:
{
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
@@ -5757,7 +5721,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
op = 1;
shift = 0;
do_shiftd:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
@@ -5921,7 +5885,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0c: /* fldenv mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x0d: /* fldcw mem */
tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
@@ -5931,7 +5895,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x0e: /* fnstenv mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
@@ -5952,12 +5916,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x2c: /* frstor mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x2e: /* fnsave mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
@@ -6304,11 +6268,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa4: /* movsS */
case 0xa5:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6318,11 +6278,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xaa: /* stosS */
case 0xab:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6331,10 +6287,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xac: /* lodsS */
case 0xad:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
@@ -6343,10 +6296,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xae: /* scasS */
case 0xaf:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6358,10 +6308,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xa6: /* cmpsS */
case 0xa7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
@@ -6372,10 +6319,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x6c: /* insS */
case 0x6d:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
@@ -6390,10 +6334,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x6e: /* outsS */
case 0x6f:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
@@ -6412,10 +6353,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xe4:
case 0xe5:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6431,10 +6369,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xe6:
case 0xe7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
@@ -6452,10 +6387,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xec:
case 0xed:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6471,10 +6403,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xee:
case 0xef:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
@@ -6497,10 +6426,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = cpu_ldsw_code(env, s->pc);
s->pc += 2;
gen_pop_T0(s);
- if (CODE64(s) && s->dflag)
- s->dflag = 2;
- gen_stack_update(s, val + (2 << s->dflag));
- if (s->dflag == 0) {
+ if (CODE64(s) && dflag != MO_16) {
+ dflag = MO_64;
+ }
+ gen_stack_update(s, val + (1 << dflag));
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -6509,7 +6439,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc3: /* ret */
gen_pop_T0(s);
gen_pop_update(s);
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
gen_op_jmp_T0();
@@ -6522,21 +6452,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag),
+ gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
gen_op_jmp_T0();
/* pop selector */
- gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_addl_A0_im(1 << dflag);
+ gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
- gen_stack_update(s, val + (4 << s->dflag));
+ gen_stack_update(s, val + (2 << dflag));
}
gen_eob(s);
break;
@@ -6547,19 +6477,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
if (!s->pe) {
/* real mode */
- gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
set_cc_op(s, CC_OP_EFLAGS);
} else if (s->vm86) {
if (s->iopl != 3) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
set_cc_op(s, CC_OP_EFLAGS);
}
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag),
+ gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
set_cc_op(s, CC_OP_EFLAGS);
}
@@ -6567,16 +6497,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0xe8: /* call im */
{
- if (dflag)
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
- else
+ } else {
tval = (int16_t)insn_get(env, s, MO_16);
+ }
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
- else if(!CODE64(s))
+ } else if (!CODE64(s)) {
tval &= 0xffffffff;
+ }
tcg_gen_movi_tl(cpu_T[0], next_eip);
gen_push_T0(s);
gen_jmp(s, tval);
@@ -6588,7 +6520,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
@@ -6597,15 +6529,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
goto do_lcall;
case 0xe9: /* jmp im */
- if (dflag)
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
- else
+ } else {
tval = (int16_t)insn_get(env, s, MO_16);
+ }
tval += s->pc - s->cs_base;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
- else if(!CODE64(s))
+ } else if (!CODE64(s)) {
tval &= 0xffffffff;
+ }
gen_jmp(s, tval);
break;
case 0xea: /* ljmp im */
@@ -6614,7 +6548,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
@@ -6625,15 +6559,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xeb: /* jmp Jb */
tval = (int8_t)insn_get(env, s, MO_8);
tval += s->pc - s->cs_base;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
gen_jmp(s, tval);
break;
case 0x70 ... 0x7f: /* jcc Jb */
tval = (int8_t)insn_get(env, s, MO_8);
goto do_jcc;
case 0x180 ... 0x18f: /* jcc Jv */
- if (dflag) {
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
} else {
tval = (int16_t)insn_get(env, s, MO_16);
@@ -6641,8 +6576,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
do_jcc:
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
gen_jcc(s, b, tval, next_eip);
break;
@@ -6655,7 +6591,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_cmovcc1(env, s, ot, b, modrm, reg);
@@ -6680,7 +6616,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_pop_T0(s);
if (s->cpl == 0) {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK |
@@ -6695,7 +6631,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
} else {
if (s->cpl <= s->iopl) {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK |
AC_MASK |
@@ -6712,7 +6648,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
& 0xffff));
}
} else {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK)));
@@ -6772,7 +6708,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/************************/
/* bit operations */
case 0x1ba: /* bt/bts/btr/btc Gv, im */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
op = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -6803,7 +6739,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1bb: /* btc */
op = 3;
do_btx:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
@@ -6861,7 +6797,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1bc: /* bsf / tzcnt */
case 0x1bd: /* bsr / lzcnt */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
@@ -7060,7 +6996,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x62: /* bound */
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
@@ -7079,7 +7015,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c8 ... 0x1cf: /* bswap reg */
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
gen_op_mov_TN_reg(MO_64, 0, reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_T0(MO_64, reg);
@@ -7109,7 +7045,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tval = (int8_t)insn_get(env, s, MO_8);
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16)
tval &= 0xffff;
l1 = gen_new_label();
@@ -7195,7 +7131,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_sysexit(cpu_env, tcg_const_i32(dflag));
+ gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1));
gen_eob(s);
}
break;
@@ -7213,7 +7149,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (s->lma) {
set_cc_op(s, CC_OP_EFLAGS);
@@ -7247,9 +7183,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
- ot = MO_16;
- if (mod == 3)
- ot += s->dflag;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 2: /* lldt */
@@ -7270,9 +7204,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
- ot = MO_16;
- if (mod == 3)
- ot += s->dflag;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 3: /* ltr */
@@ -7320,7 +7252,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
@@ -7376,7 +7308,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
@@ -7477,7 +7409,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
if (op == 2) {
@@ -7580,7 +7512,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s)) {
int d_ot;
/* d_ot is the size of destination */
- d_ot = dflag + MO_16;
+ d_ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
@@ -7654,7 +7586,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
TCGv t0;
if (!s->pe || s->vm86)
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
@@ -7790,7 +7722,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x1c3: /* MOVNTI reg, mem */
if (!(s->cpuid_features & CPUID_SSE2))
goto illegal_op;
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
@@ -7815,7 +7747,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
+ gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
break;
case 1: /* fxrstor */
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
@@ -7828,8 +7760,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fxrstor(cpu_env, cpu_A0,
- tcg_const_i32((s->dflag == 2)));
+ gen_helper_fxrstor(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
break;
case 2: /* ldmxcsr */
case 3: /* stmxcsr */
@@ -7899,12 +7830,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
- if (s->prefix & PREFIX_DATA)
+ if (s->prefix & PREFIX_DATA) {
ot = MO_16;
- else if (s->dflag != 2)
- ot = MO_32;
- else
- ot = MO_64;
+ } else {
+ ot = mo_64_32(dflag);
+ }
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 38/60] target-i386: Tidy addr16 code in gen_lea_modrm
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (36 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 37/60] target-i386: Change dflag " Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 39/60] target-i386: Combine gen_push_T* into gen_push_v Richard Henderson
` (22 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Unlike the addr32, there was no bug. But we can use the same
technique to reduce the number of TCG ops.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 34 ++++++++++++++++------------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index a12f159..9cda7dc 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2028,51 +2028,49 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
break;
default:
case 2:
- disp = cpu_lduw_code(env, s->pc);
+ disp = (int16_t)cpu_lduw_code(env, s->pc);
s->pc += 2;
break;
}
- switch(rm) {
+
+ sum = cpu_A0;
+ switch (rm) {
case 0:
- gen_op_movl_A0_reg(R_EBX);
- gen_op_addl_A0_reg_sN(0, R_ESI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_ESI]);
break;
case 1:
- gen_op_movl_A0_reg(R_EBX);
- gen_op_addl_A0_reg_sN(0, R_EDI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_EDI]);
break;
case 2:
- gen_op_movl_A0_reg(R_EBP);
- gen_op_addl_A0_reg_sN(0, R_ESI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_ESI]);
break;
case 3:
- gen_op_movl_A0_reg(R_EBP);
- gen_op_addl_A0_reg_sN(0, R_EDI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_EDI]);
break;
case 4:
- gen_op_movl_A0_reg(R_ESI);
+ sum = cpu_regs[R_ESI];
break;
case 5:
- gen_op_movl_A0_reg(R_EDI);
+ sum = cpu_regs[R_EDI];
break;
case 6:
- gen_op_movl_A0_reg(R_EBP);
+ sum = cpu_regs[R_EBP];
break;
default:
case 7:
- gen_op_movl_A0_reg(R_EBX);
+ sum = cpu_regs[R_EBX];
break;
}
- if (disp != 0)
- gen_op_addl_A0_im(disp);
+ tcg_gen_addi_tl(cpu_A0, sum, disp);
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
no_rm:
if (must_add_seg) {
if (override < 0) {
- if (rm == 2 || rm == 3 || rm == 6)
+ if (rm == 2 || rm == 3 || rm == 6) {
override = R_SS;
- else
+ } else {
override = R_DS;
+ }
}
gen_op_addl_A0_seg(s, override);
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 39/60] target-i386: Combine gen_push_T* into gen_push_v
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (37 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 38/60] target-i386: Tidy addr16 code in gen_lea_modrm Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 40/60] target_i386: Clean up gen_pop_T0 Richard Henderson
` (21 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Reduce ifdefs, share more code between paths, reduce the number of TCG
ops generated.
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 106 +++++++++++++++---------------------------------
1 file changed, 32 insertions(+), 74 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9cda7dc..4289d49 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2383,78 +2383,36 @@ static inline void gen_stack_update(DisasContext *s, int addend)
}
}
-/* generate a push. It depends on ss32, addseg and dflag */
-static void gen_push_T0(DisasContext *s)
+/* Generate a push. It depends on ss32, addseg and dflag. */
+static void gen_push_v(DisasContext *s, TCGv val)
{
-#ifdef TARGET_X86_64
- if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- if (s->dflag != MO_16) {
- gen_op_addq_A0_im(-8);
- gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0);
- } else {
- gen_op_addq_A0_im(-2);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
- }
- gen_op_mov_reg_A0(MO_64, R_ESP);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-1 << s->dflag);
- if (s->ss32) {
- if (s->addseg) {
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
- if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(MO_32, R_ESP);
- else
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
- }
-}
+ TCGMemOp a_ot, d_ot = mo_pushpop(s, s->dflag);
+ int size = 1 << d_ot;
+ TCGv new_esp = cpu_A0;
+
+ tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size);
-/* generate a push. It depends on ss32, addseg and dflag */
-/* slower version for T1, only used for call Ev */
-static void gen_push_T1(DisasContext *s)
-{
-#ifdef TARGET_X86_64
if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- if (s->dflag != MO_16) {
- gen_op_addq_A0_im(-8);
- gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
- } else {
- gen_op_addq_A0_im(-2);
- gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0);
- }
- gen_op_mov_reg_A0(MO_64, R_ESP);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-1 << s->dflag);
- if (s->ss32) {
- if (s->addseg) {
- gen_op_addl_A0_seg(s, R_SS);
- }
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
+ a_ot = MO_64;
+ } else if (s->ss32) {
+ a_ot = MO_32;
+ if (s->addseg) {
+ new_esp = cpu_tmp4;
+ tcg_gen_mov_tl(new_esp, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
+ } else {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
- gen_op_st_v(s, s->dflag, cpu_T[1], cpu_A0);
-
- if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(MO_32, R_ESP);
- else
- gen_stack_update(s, -1 << s->dflag);
+ } else {
+ a_ot = MO_16;
+ new_esp = cpu_tmp4;
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
+ tcg_gen_mov_tl(new_esp, cpu_A0);
+ gen_op_addl_A0_seg(s, R_SS);
}
+
+ gen_op_st_v(s, d_ot, val, cpu_A0);
+ gen_op_mov_reg_v(a_ot, R_ESP, new_esp);
}
/* two step pop is necessary for precise exceptions */
@@ -4982,7 +4940,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
next_eip = s->pc - s->cs_base;
tcg_gen_movi_tl(cpu_T[1], next_eip);
- gen_push_T1(s);
+ gen_push_v(s, cpu_T[1]);
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -5032,7 +4990,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
break;
case 6: /* push Ev */
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
default:
goto illegal_op;
@@ -5274,7 +5232,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* push/pop */
case 0x50 ... 0x57: /* push */
gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s));
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
ot = mo_pushpop(s, dflag);
@@ -5301,7 +5259,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
else
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x8f: /* pop Ev */
ot = mo_pushpop(s, dflag);
@@ -5354,12 +5312,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
gen_op_movl_T0_seg(b >> 3);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x1a0: /* push fs */
case 0x1a8: /* push gs */
gen_op_movl_T0_seg((b >> 3) & 7);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x07: /* pop es */
case 0x17: /* pop ss */
@@ -6508,7 +6466,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tval &= 0xffffffff;
}
tcg_gen_movi_tl(cpu_T[0], next_eip);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
gen_jmp(s, tval);
}
break;
@@ -6604,7 +6562,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_update_cc_op(s);
gen_helper_read_eflags(cpu_T[0], cpu_env);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
}
break;
case 0x9d: /* popf */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 40/60] target_i386: Clean up gen_pop_T0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (38 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 39/60] target-i386: Combine gen_push_T* into gen_push_v Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg Richard Henderson
` (20 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Reduce ifdefs, share more code between paths, reduce the number of TCG
ops generated. Avoid re-computing the size of the operation across
gen_pop_T0 and gen_pop_update.
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 84 ++++++++++++++++++++++---------------------------
1 file changed, 37 insertions(+), 47 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 4289d49..52849e1 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2416,30 +2416,30 @@ static void gen_push_v(DisasContext *s, TCGv val)
}
/* two step pop is necessary for precise exceptions */
-static void gen_pop_T0(DisasContext *s)
+static TCGMemOp gen_pop_T0(DisasContext *s)
{
-#ifdef TARGET_X86_64
+ TCGMemOp d_ot = mo_pushpop(s, s->dflag);
+ TCGv addr = cpu_A0;
+
if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_v(s, mo_pushpop(s, s->dflag), cpu_T[0], cpu_A0);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- if (s->ss32) {
- if (s->addseg)
- gen_op_addl_A0_seg(s, R_SS);
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
+ addr = cpu_regs[R_ESP];
+ } else if (!s->ss32) {
+ tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_op_addl_A0_seg(s, R_SS);
+ } else if (s->addseg) {
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_op_addl_A0_seg(s, R_SS);
+ } else {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_regs[R_ESP]);
}
+
+ gen_op_ld_v(s, d_ot, cpu_T[0], addr);
+ return d_ot;
}
-static void gen_pop_update(DisasContext *s)
+static void gen_pop_update(DisasContext *s, TCGMemOp ot)
{
- gen_stack_update(s, 1 << mo_pushpop(s, s->dflag));
+ gen_stack_update(s, 1 << ot);
}
static void gen_stack_A0(DisasContext *s)
@@ -5235,10 +5235,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
- ot = mo_pushpop(s, dflag);
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
- gen_pop_update(s);
+ gen_pop_update(s, ot);
gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
break;
case 0x60: /* pusha */
@@ -5262,13 +5261,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_push_v(s, cpu_T[0]);
break;
case 0x8f: /* pop Ev */
- ot = mo_pushpop(s, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
if (mod == 3) {
/* NOTE: order is important for pop %sp */
- gen_pop_update(s);
+ gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_T0(ot, rm);
} else {
@@ -5276,7 +5274,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->popl_esp_hack = 1 << ot;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
s->popl_esp_hack = 0;
- gen_pop_update(s);
+ gen_pop_update(s, ot);
}
break;
case 0xc8: /* enter */
@@ -5300,10 +5298,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(MO_16, 0, R_EBP);
gen_op_mov_reg_T0(MO_16, R_ESP);
}
- gen_pop_T0(s);
- ot = mo_pushpop(s, dflag);
+ ot = gen_pop_T0(s);
gen_op_mov_reg_T0(ot, R_EBP);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
break;
case 0x06: /* push es */
case 0x0e: /* push cs */
@@ -5325,9 +5322,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
reg = b >> 3;
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
if (reg == R_SS) {
/* if reg == SS, inhibit interrupts/trace. */
/* If several instructions disable interrupts, only the
@@ -5343,9 +5340,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 0x1a1: /* pop fs */
case 0x1a9: /* pop gs */
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
if (s->is_jmp) {
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -6381,23 +6378,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xc2: /* ret im */
val = cpu_ldsw_code(env, s->pc);
s->pc += 2;
- gen_pop_T0(s);
- if (CODE64(s) && dflag != MO_16) {
- dflag = MO_64;
- }
- gen_stack_update(s, val + (1 << dflag));
- if (dflag == MO_16) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- }
+ ot = gen_pop_T0(s);
+ gen_stack_update(s, val + (1 << ot));
+ /* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_T0();
gen_eob(s);
break;
case 0xc3: /* ret */
- gen_pop_T0(s);
- gen_pop_update(s);
- if (dflag == MO_16) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- }
+ ot = gen_pop_T0(s);
+ gen_pop_update(s, ot);
+ /* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -6570,7 +6560,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->vm86 && s->iopl != 3) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
if (s->cpl == 0) {
if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
@@ -6616,7 +6606,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
}
}
- gen_pop_update(s);
+ gen_pop_update(s, ot);
set_cc_op(s, CC_OP_EFLAGS);
/* abort translation because TF/AC flag may change */
gen_jmp_im(s->pc - s->cs_base);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (39 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 40/60] target_i386: Clean up gen_pop_T0 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-12-26 18:38 ` Peter Maydell
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 42/60] target-i386: Use gen_lea_v_seg in gen_lea_modrm Richard Henderson
` (19 subsequent siblings)
60 siblings, 1 reply; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case;
use this new function to implement gen_string_movl_A0_EDI,
gen_string_movl_A0_ESI, gen_add_A0_ds_seg.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 159 ++++++++++++++++--------------------------------
1 file changed, 52 insertions(+), 107 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 52849e1..02b45ef 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -440,64 +440,18 @@ static inline void gen_op_add_reg_T0(TCGMemOp size, int reg)
gen_op_mov_reg_v(size, reg, cpu_tmp0);
}
-static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
-{
- tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
- if (shift != 0)
- tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- /* For x86_64, this sets the higher half of register to zero.
- For i386, this is equivalent to a nop. */
- tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
-}
-
-static inline void gen_op_movl_A0_seg(int reg)
-{
- tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
-}
-
static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
{
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
-#ifdef TARGET_X86_64
if (CODE64(s)) {
- tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
} else {
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
-#else
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
-#endif
}
-#ifdef TARGET_X86_64
-static inline void gen_op_movq_A0_seg(int reg)
-{
- tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base));
-}
-
-static inline void gen_op_addq_A0_seg(int reg)
-{
- tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
-}
-
-static inline void gen_op_movq_A0_reg(int reg)
-{
- tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
-}
-
-static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
-{
- tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
- if (shift != 0)
- tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
-}
-#endif
-
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
@@ -523,70 +477,77 @@ static inline void gen_jmp_im(target_ulong pc)
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
}
-static inline void gen_string_movl_A0_ESI(DisasContext *s)
+/* Compute SEG:REG into A0. SEG is selected from the override segment
+ (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to
+ indicate no override. */
+static void gen_lea_v_seg(DisasContext *s, TCGv a0, int def_seg, int ovr_seg)
{
- int override;
+ TCGMemOp aflag = s->aflag;
- override = s->override;
- switch (s->aflag) {
+ switch (aflag) {
#ifdef TARGET_X86_64
case MO_64:
- if (override >= 0) {
- gen_op_movq_A0_seg(override);
- gen_op_addq_A0_reg_sN(0, R_ESI);
- } else {
- gen_op_movq_A0_reg(R_ESI);
+ if (ovr_seg < 0) {
+ tcg_gen_mov_tl(cpu_A0, a0);
+ return;
}
break;
#endif
case MO_32:
/* 32 bit address */
- if (s->addseg && override < 0)
- override = R_DS;
- if (override >= 0) {
- gen_op_movl_A0_seg(override);
- gen_op_addl_A0_reg_sN(0, R_ESI);
- } else {
- gen_op_movl_A0_reg(R_ESI);
+ if (ovr_seg < 0) {
+ if (s->addseg) {
+ ovr_seg = def_seg;
+ } else {
+ tcg_gen_ext32u_tl(cpu_A0, a0);
+ return;
+ }
}
break;
case MO_16:
- /* 16 address, always override */
- if (override < 0)
- override = R_DS;
- tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]);
- gen_op_addl_A0_seg(s, override);
+ /* 16 bit address */
+ if (ovr_seg < 0) {
+ ovr_seg = def_seg;
+ }
+ tcg_gen_ext16u_tl(cpu_A0, a0);
+ if (!s->addseg) {
+ return;
+ }
+ a0 = cpu_A0;
break;
default:
tcg_abort();
}
-}
-static inline void gen_string_movl_A0_EDI(DisasContext *s)
-{
- switch (s->aflag) {
-#ifdef TARGET_X86_64
- case MO_64:
- gen_op_movq_A0_reg(R_EDI);
- break;
-#endif
- case MO_32:
- if (s->addseg) {
- gen_op_movl_A0_seg(R_ES);
- gen_op_addl_A0_reg_sN(0, R_EDI);
+ if (ovr_seg >= 0) {
+ TCGv seg = tcg_temp_new();
+
+ tcg_gen_ld_tl(seg, cpu_env, offsetof(CPUX86State, segs[ovr_seg].base));
+
+ if (aflag == MO_64) {
+ tcg_gen_add_tl(cpu_A0, a0, seg);
+ } else if (CODE64(s)) {
+ tcg_gen_ext32u_tl(cpu_A0, a0);
+ tcg_gen_add_tl(cpu_A0, cpu_A0, seg);
} else {
- gen_op_movl_A0_reg(R_EDI);
+ tcg_gen_add_tl(cpu_A0, a0, seg);
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
- break;
- case MO_16:
- tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_EDI]);
- gen_op_addl_A0_seg(s, R_ES);
- break;
- default:
- tcg_abort();
+
+ tcg_temp_free(seg);
}
}
+static inline void gen_string_movl_A0_ESI(DisasContext *s)
+{
+ gen_lea_v_seg(s, cpu_regs[R_ESI], R_DS, s->override);
+}
+
+static inline void gen_string_movl_A0_EDI(DisasContext *s)
+{
+ gen_lea_v_seg(s, cpu_regs[R_EDI], R_ES, -1);
+}
+
static inline void gen_op_movl_T0_Dshift(TCGMemOp ot)
{
tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
@@ -2141,23 +2102,7 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
/* used for LEA and MOV AX, mem */
static void gen_add_A0_ds_seg(DisasContext *s)
{
- int override, must_add_seg;
- must_add_seg = s->addseg;
- override = R_DS;
- if (s->override >= 0) {
- override = s->override;
- must_add_seg = 1;
- }
- if (must_add_seg) {
-#ifdef TARGET_X86_64
- if (CODE64(s)) {
- gen_op_addq_A0_seg(override);
- } else
-#endif
- {
- gen_op_addl_A0_seg(s, override);
- }
- }
+ gen_lea_v_seg(s, cpu_A0, R_DS, s->override);
}
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg Richard Henderson
@ 2013-12-26 18:38 ` Peter Maydell
2013-12-26 19:31 ` Richard Henderson
0 siblings, 1 reply; 75+ messages in thread
From: Peter Maydell @ 2013-12-26 18:38 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 29 November 2013 03:00, Richard Henderson <rth@twiddle.net> wrote:
> Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case;
> use this new function to implement gen_string_movl_A0_EDI,
> gen_string_movl_A0_ESI, gen_add_A0_ds_seg.
I'm afraid I can't figure out how this code matches up with the previous
implementation of these functions. For example:
> +/* Compute SEG:REG into A0. SEG is selected from the override segment
> + (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to
> + indicate no override. */
> +static void gen_lea_v_seg(DisasContext *s, TCGv a0, int def_seg, int ovr_seg)
> {
> - int override;
> + TCGMemOp aflag = s->aflag;
>
> - override = s->override;
> - switch (s->aflag) {
> + switch (aflag) {
> #ifdef TARGET_X86_64
> case MO_64:
> - if (override >= 0) {
> - gen_op_movq_A0_seg(override);
> - gen_op_addq_A0_reg_sN(0, R_ESI);
> - } else {
> - gen_op_movq_A0_reg(R_ESI);
> + if (ovr_seg < 0) {
> + tcg_gen_mov_tl(cpu_A0, a0);
> + return;
> }
> break;
> #endif
> case MO_32:
> /* 32 bit address */
> - if (s->addseg && override < 0)
> - override = R_DS;
> - if (override >= 0) {
> - gen_op_movl_A0_seg(override);
> - gen_op_addl_A0_reg_sN(0, R_ESI);
> - } else {
> - gen_op_movl_A0_reg(R_ESI);
> + if (ovr_seg < 0) {
> + if (s->addseg) {
> + ovr_seg = def_seg;
> + } else {
> + tcg_gen_ext32u_tl(cpu_A0, a0);
> + return;
> + }
> }
> break;
> case MO_16:
> - /* 16 address, always override */
> - if (override < 0)
> - override = R_DS;
> - tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESI]);
> - gen_op_addl_A0_seg(s, override);
> + /* 16 bit address */
> + if (ovr_seg < 0) {
> + ovr_seg = def_seg;
> + }
> + tcg_gen_ext16u_tl(cpu_A0, a0);
> + if (!s->addseg) {
> + return;
> + }
The old MO_16 code for gen_string_movl* doesn't care
about s->addseg, and always performs an add of a segment.
This new code might stop without doing the addition.
> + a0 = cpu_A0;
This is also pretty confusing -- we have a parameter "a0"
which isn't the same thing as cpu_A0, and in this case
statement sometimes cpu_A0 is the result we're calculating
based on a0, and sometimes we don't touch cpu_A0 at
all and rely on following code to set it up, and in this case
we use cpu_A0 as a random temporary and then assign
it to a0...
> break;
> default:
> tcg_abort();
> }
> -}
I also find the handling of "ovr_seg < 0" pretty hard to read
in the new code -- the code for "we don't need to add a
segment" and "we do need to add a segment" is all mixed
up together, half the cases in the switch statement return
early and half fall out to maybe go through the code below,
and the code below is only for the "adding a segment" part.
I suspect it would be clearer if it was written:
if (ovr_seg < 0 &&
(s->aflag == MO_16 || (s->aflag == MO_32 && s->addseg))) {
ovr_seg = def_seg;
}
if (ovr_seg < 0) {
/* generate code for no segment add */
} else {
/* generate code for segment add */
}
thanks
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg
2013-12-26 18:38 ` Peter Maydell
@ 2013-12-26 19:31 ` Richard Henderson
2013-12-26 21:27 ` Peter Maydell
0 siblings, 1 reply; 75+ messages in thread
From: Richard Henderson @ 2013-12-26 19:31 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 12/26/2013 10:38 AM, Peter Maydell wrote:
> The old MO_16 code for gen_string_movl* doesn't care
> about s->addseg, and always performs an add of a segment.
> This new code might stop without doing the addition.
The only time s->addseg will be false in 16-bit mode is during translation of
LEA. I do need the addseg check there for LEA cleanup, but this change should
not affect gen_string_movl.
>> + a0 = cpu_A0;
>
> This is also pretty confusing -- we have a parameter "a0"
> which isn't the same thing as cpu_A0, and in this case
> statement sometimes cpu_A0 is the result we're calculating
> based on a0, and sometimes we don't touch cpu_A0 at
> all and rely on following code to set it up, and in this case
> we use cpu_A0 as a random temporary and then assign
> it to a0...
While I can agree that a0 vs cpu_A0 might be a tad confusing, a0 is always the
current input address, and cpu_A0 is always the output address.
I disagree with the characterization "random temporary". Using the output as a
temporary in computing the output is totally sensible, given that our most
popular host platform is 2-address.
> I also find the handling of "ovr_seg < 0" pretty hard to read
> in the new code -- the code for "we don't need to add a
> segment" and "we do need to add a segment" is all mixed
> up together, half the cases in the switch statement return
> early and half fall out to maybe go through the code below,
> and the code below is only for the "adding a segment" part.
>
> I suspect it would be clearer if it was written:
>
> if (ovr_seg < 0 &&
> (s->aflag == MO_16 || (s->aflag == MO_32 && s->addseg))) {
> ovr_seg = def_seg;
> }
> if (ovr_seg < 0) {
> /* generate code for no segment add */
> } else {
> /* generate code for segment add */
> }
Really? I honestly find that harder to read, because that first condition is
so complicated. Better to have it split out in the swtch statement where we're
already doing special things for M_16, M_32, and M_64.
r~
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg
2013-12-26 19:31 ` Richard Henderson
@ 2013-12-26 21:27 ` Peter Maydell
2013-12-26 21:31 ` Peter Maydell
2013-12-27 14:49 ` Richard Henderson
0 siblings, 2 replies; 75+ messages in thread
From: Peter Maydell @ 2013-12-26 21:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 26 December 2013 19:31, Richard Henderson <rth@twiddle.net> wrote:
> On 12/26/2013 10:38 AM, Peter Maydell wrote:
>> The old MO_16 code for gen_string_movl* doesn't care
>> about s->addseg, and always performs an add of a segment.
>> This new code might stop without doing the addition.
>
> The only time s->addseg will be false in 16-bit mode is during translation of
> LEA. I do need the addseg check there for LEA cleanup, but this change should
> not affect gen_string_movl.
Oh, is that the bit that does:
val = s->addseg;
s->addseg = 0;
gen_lea_modrm(env, s, modrm);
s->addseg = val;
? I think we should get rid of that -- s->addseg should always
mean "we can do the segment-base-is-zero optimization",
it shouldn't be a secret hidden parameter to the gen_lea functions
saying "don't do this addition".
> I disagree with the characterization "random temporary". Using the output as a
> temporary in computing the output is totally sensible, given that our most
> popular host platform is 2-address.
This is the kind of thing that in an ideal world the register allocator
would deal with. The tcg/README optimisation suggestions
don't say anything about preferring to use X,X,Y rather than X,Y,Z
ops where possible, and typically allocating and using a special
purpose temp is more readable code.
>> I also find the handling of "ovr_seg < 0" pretty hard to read
>> in the new code -- the code for "we don't need to add a
>> segment" and "we do need to add a segment" is all mixed
>> up together, half the cases in the switch statement return
>> early and half fall out to maybe go through the code below,
>> and the code below is only for the "adding a segment" part.
>>
>> I suspect it would be clearer if it was written:
>>
>> if (ovr_seg < 0 &&
>> (s->aflag == MO_16 || (s->aflag == MO_32 && s->addseg))) {
>> ovr_seg = def_seg;
>> }
>> if (ovr_seg < 0) {
>> /* generate code for no segment add */
>> } else {
>> /* generate code for segment add */
>> }
>
> Really? I honestly find that harder to read, because that first condition is
> so complicated. Better to have it split out in the swtch statement where we're
> already doing special things for M_16, M_32, and M_64.
I'm trying to separate out "what are we doing?" ie "do we need to
do no segment add, segment add of specified segment, or segment
add of default segment?" from "how do we do it" ie "emit these
tcg instructions".
More generally, it's pretty unclear to me why we're handling
"use default segment register for instruction" (ie ovr_seg == -1)
differently for the three cases. The whole addseg
business appears to be a combination of poorly documented
optimization and dodgy backdoor for the lea case as above.
Why is it OK to skip the addition of the base address for ES
(in the movl_A0_EDI case) when the comment for addseg says
it only applies to CS/DS/ES? Why is it not OK to skip the addition
of the base address for CS/DS/ES if it was specified by an
override prefix rather than being the default for the insn?
It seems to me that we ought to try to get this code to a
point where it looks more like:
if (ovr_seg < 0) {
ovr_seg = def_seg;
}
emit code to get address;
if (!segment_base_guaranteed_zero(s, ovr_seg)) {
emit code to add base to address;
}
where segment_base_guaranteed_zero() is a helper
function like:
bool segment_base_guaranteed_zero(s, seg) {
/* Return true if we can guarantee at translate time that
* the base address of the specified segment is zero
* (and thus can skip emitting code to add it)
*/
return (!s->addseg &&
(seg == R_CS || seg == R_DS || seg == R_SS));
}
thanks
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg
2013-12-26 21:27 ` Peter Maydell
@ 2013-12-26 21:31 ` Peter Maydell
2013-12-27 14:49 ` Richard Henderson
1 sibling, 0 replies; 75+ messages in thread
From: Peter Maydell @ 2013-12-26 21:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 26 December 2013 21:27, Peter Maydell <peter.maydell@linaro.org> wrote:
> Why is it OK to skip the addition of the base address for ES
> (in the movl_A0_EDI case) when the comment for addseg says
> it only applies to CS/DS/ES?
Scratch that, misread of the comment. addseg applies to DS/ES/SS.
> Why is it not OK to skip the addition
> of the base address for CS/DS/ES if it was specified by an
> override prefix rather than being the default for the insn?
This still applies though.
> It seems to me that we ought to try to get this code to a
> point where it looks more like:
> if (ovr_seg < 0) {
> ovr_seg = def_seg;
> }
> emit code to get address;
> if (!segment_base_guaranteed_zero(s, ovr_seg)) {
> emit code to add base to address;
> }
>
> where segment_base_guaranteed_zero() is a helper
> function like:
> bool segment_base_guaranteed_zero(s, seg) {
> /* Return true if we can guarantee at translate time that
> * the base address of the specified segment is zero
> * (and thus can skip emitting code to add it)
> */
> return (!s->addseg &&
> (seg == R_CS || seg == R_DS || seg == R_SS));
s/R_CS/R_ES/;
> }
thanks
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg
2013-12-26 21:27 ` Peter Maydell
2013-12-26 21:31 ` Peter Maydell
@ 2013-12-27 14:49 ` Richard Henderson
2013-12-27 16:06 ` Peter Maydell
1 sibling, 1 reply; 75+ messages in thread
From: Richard Henderson @ 2013-12-27 14:49 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 12/26/2013 01:27 PM, Peter Maydell wrote:
>> The only time s->addseg will be false in 16-bit mode is during translation of
>> LEA. I do need the addseg check there for LEA cleanup, but this change should
>> not affect gen_string_movl.
>
> Oh, is that the bit that does:
>
> val = s->addseg;
> s->addseg = 0;
> gen_lea_modrm(env, s, modrm);
> s->addseg = val;
>
> ? I think we should get rid of that -- s->addseg should always
> mean "we can do the segment-base-is-zero optimization",
> it shouldn't be a secret hidden parameter to the gen_lea functions
> saying "don't do this addition".
Perhaps. I'd rather do that as follow-up, since lea_v_seg isn't the top-level
function called for LEA. And if we clean up addseg, we might as well clean up
popl_esp_hack as well.
How about a comment for now?
>> I disagree with the characterization "random temporary". Using the output as a
>> temporary in computing the output is totally sensible, given that our most
>> popular host platform is 2-address.
>
> This is the kind of thing that in an ideal world the register allocator
> would deal with. The tcg/README optimisation suggestions
> don't say anything about preferring to use X,X,Y rather than X,Y,Z
> ops where possible, and typically allocating and using a special
> purpose temp is more readable code.
I agree that a real register allocator would handle it.
I disagree that a special purpose temp would result in more readable code,
since then we'd need to add *more* code to deallocate it after the other
arithmetic.
> More generally, it's pretty unclear to me why we're handling
> "use default segment register for instruction" (ie ovr_seg == -1)
> differently for the three cases.
Because the handling of segments is fundamentally different in each of the
three cpu modes?
> Why is it OK to skip the addition of the base address for ES
> (in the movl_A0_EDI case) when the comment for addseg says
> it only applies to CS/DS/ES?
Err... when are we skipping the addition in gen_string_movl_A0_EDI? We pass in
R_ES as the segment register to use...
> It seems to me that we ought to try to get this code to a
> point where it looks more like:
> if (ovr_seg < 0) {
> ovr_seg = def_seg;
> }
> emit code to get address;
> if (!segment_base_guaranteed_zero(s, ovr_seg)) {
> emit code to add base to address;
> }
>
> where segment_base_guaranteed_zero() is a helper
> function like:
> bool segment_base_guaranteed_zero(s, seg) {
> /* Return true if we can guarantee at translate time that
> * the base address of the specified segment is zero
> * (and thus can skip emitting code to add it)
> */
> return (!s->addseg &&
> (seg == R_CS || seg == R_DS || seg == R_SS));
> }
That does look much nicer, I agree.
r~
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg
2013-12-27 14:49 ` Richard Henderson
@ 2013-12-27 16:06 ` Peter Maydell
0 siblings, 0 replies; 75+ messages in thread
From: Peter Maydell @ 2013-12-27 16:06 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 27 December 2013 14:49, Richard Henderson <rth@twiddle.net> wrote:
> On 12/26/2013 01:27 PM, Peter Maydell wrote:
>>> The only time s->addseg will be false in 16-bit mode is during translation of
>>> LEA. I do need the addseg check there for LEA cleanup, but this change should
>>> not affect gen_string_movl.
>>
>> Oh, is that the bit that does:
>>
>> val = s->addseg;
>> s->addseg = 0;
>> gen_lea_modrm(env, s, modrm);
>> s->addseg = val;
>>
>> ? I think we should get rid of that -- s->addseg should always
>> mean "we can do the segment-base-is-zero optimization",
>> it shouldn't be a secret hidden parameter to the gen_lea functions
>> saying "don't do this addition".
>
> Perhaps. I'd rather do that as follow-up, since lea_v_seg isn't the top-level
> function called for LEA. And if we clean up addseg, we might as well clean up
> popl_esp_hack as well.
>
> How about a comment for now?
Yes, a comment is fine for now.
>> More generally, it's pretty unclear to me why we're handling
>> "use default segment register for instruction" (ie ovr_seg == -1)
>> differently for the three cases.
>
> Because the handling of segments is fundamentally different in each of the
> three cpu modes?
Well, yes, but I've been unable to match up what the
code is doing differently in the three cases with what the
Intel manual says about them. For instance the manual says
that segmentation is mostly disabled in 64 bit mode, but although
the function has a conditional on CODE64 it doesn't seem to
be suppressing the add for CS/DS/ES/SS base as I would
expect it to. Perhaps an explanatory comment with a reference
to the relevant sections of the intel docs would help?
Some of this seems to be because the code is tangling up a
bunch of things at once (like the lea backdooring of addseg
for 16 bit mode).
>> Why is it OK to skip the addition of the base address for ES
>> (in the movl_A0_EDI case) when the comment for addseg says
>> it only applies to CS/DS/ES?
>
> Err... when are we skipping the addition in gen_string_movl_A0_EDI? We pass in
> R_ES as the segment register to use...
Yeah, that was a confusion on my part.
thanks
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread
* [Qemu-devel] [PATCH v2 42/60] target-i386: Use gen_lea_v_seg in gen_lea_modrm
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (40 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 43/60] target-i386: Use gen_lea_v_seg in stack subroutines Richard Henderson
` (18 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Centralize handling of segment bases.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 82 ++++++++++++++-----------------------------------
1 file changed, 23 insertions(+), 59 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 02b45ef..c655e65 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1860,17 +1860,12 @@ static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c)
static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
{
target_long disp;
- int havesib;
- int base;
- int index;
- int scale;
- int mod, rm, code, override, must_add_seg;
+ int havesib, base, index, scale;
+ int mod, rm, code, def_seg, ovr_seg;
TCGv sum;
- override = s->override;
- must_add_seg = s->addseg;
- if (override >= 0)
- must_add_seg = 1;
+ def_seg = R_DS;
+ ovr_seg = s->override;
mod = (modrm >> 6) & 3;
rm = modrm & 7;
@@ -1940,61 +1935,34 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
}
if (TCGV_IS_UNUSED(sum)) {
tcg_gen_movi_tl(cpu_A0, disp);
- } else {
+ sum = cpu_A0;
+ } else if (disp != 0) {
tcg_gen_addi_tl(cpu_A0, sum, disp);
+ sum = cpu_A0;
}
- if (must_add_seg) {
- if (override < 0) {
- if (base == R_EBP || base == R_ESP) {
- override = R_SS;
- } else {
- override = R_DS;
- }
- }
-
- tcg_gen_ld_tl(cpu_tmp0, cpu_env,
- offsetof(CPUX86State, segs[override].base));
- if (CODE64(s)) {
- if (s->aflag == MO_32) {
- tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
- }
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- return;
- }
-
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- }
-
- if (s->aflag == MO_32) {
- tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
+ if (base == R_EBP || base == R_ESP) {
+ def_seg = R_SS;
}
break;
case MO_16:
- switch (mod) {
- case 0:
+ sum = cpu_A0;
+ if (mod == 0) {
if (rm == 6) {
disp = cpu_lduw_code(env, s->pc);
s->pc += 2;
tcg_gen_movi_tl(cpu_A0, disp);
- rm = 0; /* avoid SS override */
- goto no_rm;
- } else {
- disp = 0;
+ break;
}
- break;
- case 1:
+ disp = 0;
+ } else if (mod == 1) {
disp = (int8_t)cpu_ldub_code(env, s->pc++);
- break;
- default:
- case 2:
+ } else {
disp = (int16_t)cpu_lduw_code(env, s->pc);
s->pc += 2;
- break;
}
- sum = cpu_A0;
switch (rm) {
case 0:
tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_ESI]);
@@ -2004,9 +1972,11 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
break;
case 2:
tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_ESI]);
+ def_seg = R_SS;
break;
case 3:
tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_EDI]);
+ def_seg = R_SS;
break;
case 4:
sum = cpu_regs[R_ESI];
@@ -2016,30 +1986,24 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
break;
case 6:
sum = cpu_regs[R_EBP];
+ def_seg = R_SS;
break;
default:
case 7:
sum = cpu_regs[R_EBX];
break;
}
- tcg_gen_addi_tl(cpu_A0, sum, disp);
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- no_rm:
- if (must_add_seg) {
- if (override < 0) {
- if (rm == 2 || rm == 3 || rm == 6) {
- override = R_SS;
- } else {
- override = R_DS;
- }
- }
- gen_op_addl_A0_seg(s, override);
+ if (disp != 0) {
+ tcg_gen_addi_tl(cpu_A0, sum, disp);
+ sum = cpu_A0;
}
break;
default:
tcg_abort();
}
+
+ gen_lea_v_seg(s, sum, def_seg, ovr_seg);
}
static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 43/60] target-i386: Use gen_lea_v_seg in stack subroutines
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (41 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 42/60] target-i386: Use gen_lea_v_seg in gen_lea_modrm Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 44/60] target-i386: Tidy cpu_regs initialization Richard Henderson
` (17 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
I.e. gen_push_v, gen_pop_T0, gen_stack_A0.
More centralization of handling of segment bases.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 49 +++++++++++++++----------------------------------
1 file changed, 15 insertions(+), 34 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c655e65..07dac7c 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -480,10 +480,9 @@ static inline void gen_jmp_im(target_ulong pc)
/* Compute SEG:REG into A0. SEG is selected from the override segment
(OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to
indicate no override. */
-static void gen_lea_v_seg(DisasContext *s, TCGv a0, int def_seg, int ovr_seg)
+static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,
+ int def_seg, int ovr_seg)
{
- TCGMemOp aflag = s->aflag;
-
switch (aflag) {
#ifdef TARGET_X86_64
case MO_64:
@@ -540,12 +539,12 @@ static void gen_lea_v_seg(DisasContext *s, TCGv a0, int def_seg, int ovr_seg)
static inline void gen_string_movl_A0_ESI(DisasContext *s)
{
- gen_lea_v_seg(s, cpu_regs[R_ESI], R_DS, s->override);
+ gen_lea_v_seg(s, s->aflag, cpu_regs[R_ESI], R_DS, s->override);
}
static inline void gen_string_movl_A0_EDI(DisasContext *s)
{
- gen_lea_v_seg(s, cpu_regs[R_EDI], R_ES, -1);
+ gen_lea_v_seg(s, s->aflag, cpu_regs[R_EDI], R_ES, -1);
}
static inline void gen_op_movl_T0_Dshift(TCGMemOp ot)
@@ -2003,7 +2002,7 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm)
tcg_abort();
}
- gen_lea_v_seg(s, sum, def_seg, ovr_seg);
+ gen_lea_v_seg(s, s->aflag, sum, def_seg, ovr_seg);
}
static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
@@ -2066,7 +2065,7 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
/* used for LEA and MOV AX, mem */
static void gen_add_A0_ds_seg(DisasContext *s)
{
- gen_lea_v_seg(s, cpu_A0, R_DS, s->override);
+ gen_lea_v_seg(s, s->aflag, cpu_A0, R_DS, s->override);
}
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
@@ -2303,21 +2302,13 @@ static void gen_push_v(DisasContext *s, TCGv val)
if (CODE64(s)) {
a_ot = MO_64;
- } else if (s->ss32) {
- a_ot = MO_32;
+ } else {
+ a_ot = s->ss32 ? MO_32 : MO_16;
if (s->addseg) {
new_esp = cpu_tmp4;
tcg_gen_mov_tl(new_esp, cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- } else {
- tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
- } else {
- a_ot = MO_16;
- new_esp = cpu_tmp4;
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- tcg_gen_mov_tl(new_esp, cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
+ gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
}
gen_op_st_v(s, d_ot, val, cpu_A0);
@@ -2328,37 +2319,27 @@ static void gen_push_v(DisasContext *s, TCGv val)
static TCGMemOp gen_pop_T0(DisasContext *s)
{
TCGMemOp d_ot = mo_pushpop(s, s->dflag);
- TCGv addr = cpu_A0;
+ TCGv addr;
if (CODE64(s)) {
addr = cpu_regs[R_ESP];
- } else if (!s->ss32) {
- tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESP]);
- gen_op_addl_A0_seg(s, R_SS);
- } else if (s->addseg) {
- tcg_gen_mov_tl(cpu_A0, cpu_regs[R_ESP]);
- gen_op_addl_A0_seg(s, R_SS);
} else {
- tcg_gen_ext32u_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1);
+ addr = cpu_A0;
}
gen_op_ld_v(s, d_ot, cpu_T[0], addr);
return d_ot;
}
-static void gen_pop_update(DisasContext *s, TCGMemOp ot)
+static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)
{
gen_stack_update(s, 1 << ot);
}
-static void gen_stack_A0(DisasContext *s)
+static inline void gen_stack_A0(DisasContext *s)
{
- gen_op_movl_A0_reg(R_ESP);
- if (!s->ss32)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- if (s->addseg)
- gen_op_addl_A0_seg(s, R_SS);
+ gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1);
}
/* NOTE: wrap around in 16 bit not fully handled */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 44/60] target-i386: Tidy cpu_regs initialization
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (42 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 43/60] target-i386: Use gen_lea_v_seg in stack subroutines Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 45/60] target-i386: Access segs via TCG registers Richard Henderson
` (16 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 87 ++++++++++++++++++++-----------------------------
1 file changed, 36 insertions(+), 51 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 07dac7c..5a5c8b6 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7708,6 +7708,37 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
void optimize_flags_init(void)
{
+ static const char reg_names[CPU_NB_REGS][4] = {
+#ifdef TARGET_X86_64
+ [R_EAX] = "rax",
+ [R_EBX] = "rbx",
+ [R_ECX] = "rcx",
+ [R_EDX] = "rdx",
+ [R_ESI] = "rsi",
+ [R_EDI] = "rdi",
+ [R_EBP] = "rbp",
+ [R_ESP] = "rsp",
+ [8] = "r8",
+ [9] = "r9",
+ [10] = "r10",
+ [11] = "r11",
+ [12] = "r12",
+ [13] = "r13",
+ [14] = "r14",
+ [15] = "r15",
+#else
+ [R_EAX] = "eax",
+ [R_EBX] = "ebx",
+ [R_ECX] = "ecx",
+ [R_EDX] = "edx",
+ [R_ESI] = "esi",
+ [R_EDI] = "edi",
+ [R_EBP] = "ebp",
+ [R_ESP] = "esp",
+#endif
+ };
+ int i;
+
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, cc_op), "cc_op");
@@ -7718,57 +7749,11 @@ void optimize_flags_init(void)
cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src2),
"cc_src2");
-#ifdef TARGET_X86_64
- cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EAX]), "rax");
- cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ECX]), "rcx");
- cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDX]), "rdx");
- cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBX]), "rbx");
- cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESP]), "rsp");
- cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBP]), "rbp");
- cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESI]), "rsi");
- cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDI]), "rdi");
- cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[8]), "r8");
- cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[9]), "r9");
- cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[10]), "r10");
- cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[11]), "r11");
- cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[12]), "r12");
- cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[13]), "r13");
- cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[14]), "r14");
- cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[15]), "r15");
-#else
- cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EAX]), "eax");
- cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ECX]), "ecx");
- cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDX]), "edx");
- cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBX]), "ebx");
- cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESP]), "esp");
- cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBP]), "ebp");
- cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESI]), "esi");
- cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDI]), "edi");
-#endif
+ for (i = 0; i < CPU_NB_REGS; ++i) {
+ cpu_regs[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUX86State, regs[i]),
+ reg_names[i]);
+ }
}
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 45/60] target-i386: Access segs via TCG registers
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (43 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 44/60] target-i386: Tidy cpu_regs initialization Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 46/60] target-i386: Use gen_lea_v_seg in pusha/popa Richard Henderson
` (15 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Having segs[].base as a register significantly improves code
generation for real and protected modes, particularly for TBs
that have multiple memory references where the segment base
can be held in a hard register through the TB.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 71 ++++++++++++++++++++++++++++++-------------------
1 file changed, 43 insertions(+), 28 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 5a5c8b6..89e775e 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -65,6 +65,8 @@ static TCGv cpu_A0;
static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT;
static TCGv_i32 cpu_cc_op;
static TCGv cpu_regs[CPU_NB_REGS];
+static TCGv_i32 cpu_seg_sel[6];
+static TCGv cpu_seg_base[6];
/* local temps */
static TCGv cpu_T[2];
/* local register indexes (only used inside old micro ops) */
@@ -442,12 +444,11 @@ static inline void gen_op_add_reg_T0(TCGMemOp size, int reg)
static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
{
- tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
if (CODE64(s)) {
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_seg_base[reg]);
} else {
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_seg_base[reg]);
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
}
@@ -519,9 +520,7 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,
}
if (ovr_seg >= 0) {
- TCGv seg = tcg_temp_new();
-
- tcg_gen_ld_tl(seg, cpu_env, offsetof(CPUX86State, segs[ovr_seg].base));
+ TCGv seg = cpu_seg_base[ovr_seg];
if (aflag == MO_64) {
tcg_gen_add_tl(cpu_A0, a0, seg);
@@ -532,8 +531,6 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,
tcg_gen_add_tl(cpu_A0, a0, seg);
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
-
- tcg_temp_free(seg);
}
}
@@ -2216,18 +2213,14 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
static inline void gen_op_movl_T0_seg(int seg_reg)
{
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
- offsetof(CPUX86State,segs[seg_reg].selector));
+ tcg_gen_extu_i32_tl(cpu_T[0], cpu_seg_sel[seg_reg]);
}
static inline void gen_op_movl_seg_T0_vm(int seg_reg)
{
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
- tcg_gen_st32_tl(cpu_T[0], cpu_env,
- offsetof(CPUX86State,segs[seg_reg].selector));
- tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
- tcg_gen_st_tl(cpu_T[0], cpu_env,
- offsetof(CPUX86State,segs[seg_reg].base));
+ tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_seg_sel[seg_reg], cpu_T[0]);
+ tcg_gen_shli_tl(cpu_seg_base[seg_reg], cpu_T[0], 4);
}
/* move T0 to seg_reg and compute if the CPU state may change. Never
@@ -7297,21 +7290,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->cpl != 0) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- tcg_gen_ld_tl(cpu_T[0], cpu_env,
- offsetof(CPUX86State,segs[R_GS].base));
- tcg_gen_ld_tl(cpu_T[1], cpu_env,
- offsetof(CPUX86State,kernelgsbase));
- tcg_gen_st_tl(cpu_T[1], cpu_env,
- offsetof(CPUX86State,segs[R_GS].base));
+ tcg_gen_mov_tl(cpu_T[0], cpu_seg_base[R_GS]);
+ tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env,
+ offsetof(CPUX86State, kernelgsbase));
tcg_gen_st_tl(cpu_T[0], cpu_env,
- offsetof(CPUX86State,kernelgsbase));
+ offsetof(CPUX86State, kernelgsbase));
}
- } else
-#endif
- {
- goto illegal_op;
+ break;
}
- break;
+#endif
+ goto illegal_op;
case 1: /* rdtscp */
if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
goto illegal_op;
@@ -7737,6 +7725,22 @@ void optimize_flags_init(void)
[R_ESP] = "esp",
#endif
};
+ static const char seg_base_names[6][8] = {
+ [R_CS] = "cs_base",
+ [R_DS] = "ds_base",
+ [R_ES] = "es_base",
+ [R_FS] = "fs_base",
+ [R_GS] = "gs_base",
+ [R_SS] = "ss_base",
+ };
+ static const char seg_sel_names[6][8] = {
+ [R_CS] = "cs_sel",
+ [R_DS] = "ds_sel",
+ [R_ES] = "es_sel",
+ [R_FS] = "fs_sel",
+ [R_GS] = "gs_sel",
+ [R_SS] = "ss_sel",
+ };
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
@@ -7754,6 +7758,17 @@ void optimize_flags_init(void)
offsetof(CPUX86State, regs[i]),
reg_names[i]);
}
+
+ for (i = 0; i < 6; ++i) {
+ cpu_seg_base[i]
+ = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUX86State, segs[i].base),
+ seg_base_names[i]);
+ cpu_seg_sel[i]
+ = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUX86State, segs[i].selector),
+ seg_sel_names[i]);
+ }
}
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 46/60] target-i386: Use gen_lea_v_seg in pusha/popa
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (44 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 45/60] target-i386: Access segs via TCG registers Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 47/60] target-i386: Rewrite gen_enter inline Richard Henderson
` (14 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
More centralization of handling of segment bases.
Also fixes the note about 16-bit wrap around not fully handled.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 50 +++++++++++++++++++++++--------------------------
1 file changed, 23 insertions(+), 27 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 89e775e..a4f38ab 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2335,45 +2335,41 @@ static inline void gen_stack_A0(DisasContext *s)
gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1);
}
-/* NOTE: wrap around in 16 bit not fully handled */
static void gen_pusha(DisasContext *s)
{
+ TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;
+ TCGMemOp d_ot = s->dflag;
+ int size = 1 << d_ot;
int i;
- gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-8 << s->dflag);
- if (!s->ss32)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- if (s->addseg)
- gen_op_addl_A0_seg(s, R_SS);
- for(i = 0;i < 8; i++) {
- gen_op_mov_TN_reg(MO_32, 0, 7 - i);
- gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
- gen_op_addl_A0_im(1 << s->dflag);
+
+ for (i = 0; i < 8; i++) {
+ tcg_gen_addi_tl(cpu_A0, cpu_regs[R_ESP], (i - 8) * size);
+ gen_lea_v_seg(s, s_ot, cpu_A0, R_SS, -1);
+ gen_op_st_v(s, d_ot, cpu_regs[7 - i], cpu_A0);
}
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+
+ gen_stack_update(s, -8 * size);
}
-/* NOTE: wrap around in 16 bit not fully handled */
static void gen_popa(DisasContext *s)
{
+ TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;
+ TCGMemOp d_ot = s->dflag;
+ int size = 1 << d_ot;
int i;
- gen_op_movl_A0_reg(R_ESP);
- if (!s->ss32)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 8 << s->dflag);
- if (s->addseg)
- gen_op_addl_A0_seg(s, R_SS);
- for(i = 0;i < 8; i++) {
+
+ for (i = 0; i < 8; i++) {
/* ESP is not reloaded */
- if (i != 3) {
- gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(s->dflag, 7 - i);
+ if (7 - i == R_ESP) {
+ continue;
}
- gen_op_addl_A0_im(1 << s->dflag);
+ tcg_gen_addi_tl(cpu_A0, cpu_regs[R_ESP], i * size);
+ gen_lea_v_seg(s, s_ot, cpu_A0, R_SS, -1);
+ gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0);
+ gen_op_mov_reg_T0(d_ot, 7 - i);
}
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+
+ gen_stack_update(s, 8 * size);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 47/60] target-i386: Rewrite gen_enter inline
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (45 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 46/60] target-i386: Use gen_lea_v_seg in pusha/popa Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 48/60] target-i386: Introduce mo_stacksize Richard Henderson
` (13 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Use gen_lea_v_seg for centralized segment base knowledge. Unify
code across 32- and 64-bit. Fix note about "must save state"
before using the out-of-line helpers.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/helper.h | 4 ---
target-i386/seg_helper.c | 68 -------------------------------------
target-i386/translate.c | 88 +++++++++++++++++++-----------------------------
3 files changed, 34 insertions(+), 126 deletions(-)
diff --git a/target-i386/helper.h b/target-i386/helper.h
index 3775abe..c8acc64 100644
--- a/target-i386/helper.h
+++ b/target-i386/helper.h
@@ -45,10 +45,6 @@ DEF_HELPER_1(clts, void, env)
DEF_HELPER_3(movl_drN_T0, void, env, int, tl)
DEF_HELPER_2(invlpg, void, env, tl)
-DEF_HELPER_4(enter_level, void, env, int, int, tl)
-#ifdef TARGET_X86_64
-DEF_HELPER_4(enter64_level, void, env, int, int, tl)
-#endif
DEF_HELPER_1(sysenter, void, env)
DEF_HELPER_2(sysexit, void, env, int)
#ifdef TARGET_X86_64
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index e789102..115937c 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -1268,74 +1268,6 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw);
}
-void helper_enter_level(CPUX86State *env, int level, int data32,
- target_ulong t1)
-{
- target_ulong ssp;
- uint32_t esp_mask, esp, ebp;
-
- esp_mask = get_sp_mask(env->segs[R_SS].flags);
- ssp = env->segs[R_SS].base;
- ebp = env->regs[R_EBP];
- esp = env->regs[R_ESP];
- if (data32) {
- /* 32 bit */
- esp -= 4;
- while (--level) {
- esp -= 4;
- ebp -= 4;
- cpu_stl_data(env, ssp + (esp & esp_mask),
- cpu_ldl_data(env, ssp + (ebp & esp_mask)));
- }
- esp -= 4;
- cpu_stl_data(env, ssp + (esp & esp_mask), t1);
- } else {
- /* 16 bit */
- esp -= 2;
- while (--level) {
- esp -= 2;
- ebp -= 2;
- cpu_stw_data(env, ssp + (esp & esp_mask),
- cpu_lduw_data(env, ssp + (ebp & esp_mask)));
- }
- esp -= 2;
- cpu_stw_data(env, ssp + (esp & esp_mask), t1);
- }
-}
-
-#ifdef TARGET_X86_64
-void helper_enter64_level(CPUX86State *env, int level, int data64,
- target_ulong t1)
-{
- target_ulong esp, ebp;
-
- ebp = env->regs[R_EBP];
- esp = env->regs[R_ESP];
-
- if (data64) {
- /* 64 bit */
- esp -= 8;
- while (--level) {
- esp -= 8;
- ebp -= 8;
- cpu_stq_data(env, esp, cpu_ldq_data(env, ebp));
- }
- esp -= 8;
- cpu_stq_data(env, esp, t1);
- } else {
- /* 16 bit */
- esp -= 2;
- while (--level) {
- esp -= 2;
- ebp -= 2;
- cpu_stw_data(env, esp, cpu_lduw_data(env, ebp));
- }
- esp -= 2;
- cpu_stw_data(env, esp, t1);
- }
-}
-#endif
-
void helper_lldt(CPUX86State *env, int selector)
{
SegmentCache *dt;
diff --git a/target-i386/translate.c b/target-i386/translate.c
index a4f38ab..fa707c1 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -442,17 +442,6 @@ static inline void gen_op_add_reg_T0(TCGMemOp size, int reg)
gen_op_mov_reg_v(size, reg, cpu_tmp0);
}
-static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
-{
- if (CODE64(s)) {
- tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_seg_base[reg]);
- } else {
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_seg_base[reg]);
- tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
- }
-}
-
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE);
@@ -2374,51 +2363,42 @@ static void gen_popa(DisasContext *s)
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
- TCGMemOp ot = mo_pushpop(s, s->dflag);
- int opsize = 1 << ot;
+ TCGMemOp d_ot = mo_pushpop(s, s->dflag);
+ TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;
+ int size = 1 << d_ot;
- level &= 0x1f;
-#ifdef TARGET_X86_64
- if (CODE64(s)) {
- gen_op_movl_A0_reg(R_ESP);
- gen_op_addq_A0_im(-opsize);
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
-
- /* push bp */
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
- if (level) {
- /* XXX: must save state */
- gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
- tcg_const_i32((ot == MO_64)),
- cpu_T[1]);
- }
- gen_op_mov_reg_T1(ot, R_EBP);
- tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(MO_64, R_ESP);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-opsize);
- if (!s->ss32)
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- if (s->addseg)
- gen_op_addl_A0_seg(s, R_SS);
- /* push bp */
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
- if (level) {
- /* XXX: must save state */
- gen_helper_enter_level(cpu_env, tcg_const_i32(level),
- tcg_const_i32(s->dflag - 1),
- cpu_T[1]);
- }
- gen_op_mov_reg_T1(ot, R_EBP);
- tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+ /* Push BP; compute FrameTemp into T1. */
+ tcg_gen_subi_tl(cpu_T[1], cpu_regs[R_ESP], size);
+ gen_lea_v_seg(s, a_ot, cpu_T[1], R_SS, -1);
+ gen_op_st_v(s, d_ot, cpu_regs[R_EBP], cpu_A0);
+
+ level &= 31;
+ if (level != 0) {
+ int i;
+
+ /* Copy level-1 pointers from the previous frame. */
+ for (i = 1; i < level; ++i) {
+ tcg_gen_subi_tl(cpu_A0, cpu_regs[R_EBP], size * i);
+ gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
+ gen_op_ld_v(s, d_ot, cpu_tmp0, cpu_A0);
+
+ tcg_gen_subi_tl(cpu_A0, cpu_T[1], size * i);
+ gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
+ gen_op_st_v(s, d_ot, cpu_tmp0, cpu_A0);
+ }
+
+ /* Push the current FrameTemp as the last level. */
+ tcg_gen_subi_tl(cpu_A0, cpu_T[1], size * level);
+ gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
+ gen_op_st_v(s, d_ot, cpu_T[1], cpu_A0);
}
+
+ /* Copy the FrameTemp value to EBP. */
+ gen_op_mov_reg_v(a_ot, R_EBP, cpu_T[1]);
+
+ /* Compute the final value of ESP. */
+ tcg_gen_subi_tl(cpu_T[1], cpu_T[1], esp_addend + size * level);
+ gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]);
}
static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 48/60] target-i386: Introduce mo_stacksize
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (46 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 47/60] target-i386: Rewrite gen_enter inline Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 49/60] target-i386: Rewrite leave Richard Henderson
` (12 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Centralize computation of a MO_SIZE for the stack pointer.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 43 ++++++++++++++++++-------------------------
1 file changed, 18 insertions(+), 25 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index fa707c1..c5bbb5d 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -308,6 +308,12 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
}
}
+/* Select the size of the stack pointer. */
+static inline TCGMemOp mo_stacksize(DisasContext *s)
+{
+ return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;
+}
+
/* Select only size 64 else 32. Used for SSE operand sizes. */
static inline TCGMemOp mo_64_32(TCGMemOp ot)
{
@@ -2261,37 +2267,24 @@ gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
static inline void gen_stack_update(DisasContext *s, int addend)
{
-#ifdef TARGET_X86_64
- if (CODE64(s)) {
- gen_op_add_reg_im(MO_64, R_ESP, addend);
- } else
-#endif
- if (s->ss32) {
- gen_op_add_reg_im(MO_32, R_ESP, addend);
- } else {
- gen_op_add_reg_im(MO_16, R_ESP, addend);
- }
+ gen_op_add_reg_im(mo_stacksize(s), R_ESP, addend);
}
/* Generate a push. It depends on ss32, addseg and dflag. */
static void gen_push_v(DisasContext *s, TCGv val)
{
- TCGMemOp a_ot, d_ot = mo_pushpop(s, s->dflag);
+ TCGMemOp d_ot = mo_pushpop(s, s->dflag);
+ TCGMemOp a_ot = mo_stacksize(s);
int size = 1 << d_ot;
TCGv new_esp = cpu_A0;
tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size);
- if (CODE64(s)) {
- a_ot = MO_64;
- } else {
- a_ot = s->ss32 ? MO_32 : MO_16;
- if (s->addseg) {
- new_esp = cpu_tmp4;
- tcg_gen_mov_tl(new_esp, cpu_A0);
- }
- gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
+ if (s->addseg) {
+ new_esp = cpu_tmp4;
+ tcg_gen_mov_tl(new_esp, cpu_A0);
}
+ gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
gen_op_st_v(s, d_ot, val, cpu_A0);
gen_op_mov_reg_v(a_ot, R_ESP, new_esp);
@@ -2306,7 +2299,7 @@ static TCGMemOp gen_pop_T0(DisasContext *s)
if (CODE64(s)) {
addr = cpu_regs[R_ESP];
} else {
- gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1);
+ gen_lea_v_seg(s, mo_stacksize(s), cpu_regs[R_ESP], R_SS, -1);
addr = cpu_A0;
}
@@ -2321,12 +2314,12 @@ static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)
static inline void gen_stack_A0(DisasContext *s)
{
- gen_lea_v_seg(s, s->ss32 ? MO_32 : MO_16, cpu_regs[R_ESP], R_SS, -1);
+ gen_lea_v_seg(s, mo_stacksize(s), cpu_regs[R_ESP], R_SS, -1);
}
static void gen_pusha(DisasContext *s)
{
- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;
+ TCGMemOp s_ot = mo_stacksize(s);
TCGMemOp d_ot = s->dflag;
int size = 1 << d_ot;
int i;
@@ -2342,7 +2335,7 @@ static void gen_pusha(DisasContext *s)
static void gen_popa(DisasContext *s)
{
- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;
+ TCGMemOp s_ot = mo_stacksize(s);
TCGMemOp d_ot = s->dflag;
int size = 1 << d_ot;
int i;
@@ -2364,7 +2357,7 @@ static void gen_popa(DisasContext *s)
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
TCGMemOp d_ot = mo_pushpop(s, s->dflag);
- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;
+ TCGMemOp a_ot = mo_stacksize(s);
int size = 1 << d_ot;
/* Push BP; compute FrameTemp into T1. */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 49/60] target-i386: Rewrite leave
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (47 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 48/60] target-i386: Introduce mo_stacksize Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 50/60] target-i386: Remove gen_op_mov_reg_T0 Richard Henderson
` (11 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Unify the code across stack pointer widths. Fix the note about
not updating ESP before the potential exception.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 29 +++++++++++++++--------------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c5bbb5d..53e3103 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2394,6 +2394,20 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]);
}
+static void gen_leave(DisasContext *s)
+{
+ TCGMemOp d_ot = mo_pushpop(s, s->dflag);
+ TCGMemOp a_ot = mo_stacksize(s);
+
+ gen_lea_v_seg(s, a_ot, cpu_regs[R_EBP], R_SS, -1);
+ gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0);
+
+ tcg_gen_addi_tl(cpu_T[1], cpu_regs[R_EBP], 1 << d_ot);
+
+ gen_op_mov_reg_v(d_ot, R_EBP, cpu_T[0]);
+ gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]);
+}
+
static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
{
gen_update_cc_op(s);
@@ -5139,20 +5153,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
break;
case 0xc9: /* leave */
- /* XXX: exception not precise (ESP is updated before potential exception) */
- if (CODE64(s)) {
- gen_op_mov_TN_reg(MO_64, 0, R_EBP);
- gen_op_mov_reg_T0(MO_64, R_ESP);
- } else if (s->ss32) {
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_mov_reg_T0(MO_32, R_ESP);
- } else {
- gen_op_mov_TN_reg(MO_16, 0, R_EBP);
- gen_op_mov_reg_T0(MO_16, R_ESP);
- }
- ot = gen_pop_T0(s);
- gen_op_mov_reg_T0(ot, R_EBP);
- gen_pop_update(s, ot);
+ gen_leave(s);
break;
case 0x06: /* push es */
case 0x0e: /* push cs */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 50/60] target-i386: Remove gen_op_mov_reg_T0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (48 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 49/60] target-i386: Rewrite leave Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 51/60] target-i386: Remove gen_op_mov_reg_T1 Richard Henderson
` (10 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace with its definition, via Coccinelle.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 127 +++++++++++++++++++++++-------------------------
1 file changed, 61 insertions(+), 66 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 53e3103..ff0c6a9 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -366,11 +366,6 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
}
}
-static inline void gen_op_mov_reg_T0(TCGMemOp ot, int reg)
-{
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
-}
-
static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
@@ -463,7 +458,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
if (d == OR_TMP0) {
gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(idx, d);
+ gen_op_mov_reg_v(idx, d, cpu_T[0]);
}
}
@@ -1114,7 +1109,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
}
@@ -2073,11 +2068,11 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
if (reg != OR_TMP0)
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
} else {
gen_lea_modrm(env, s, modrm);
@@ -2088,7 +2083,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
if (reg != OR_TMP0)
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
}
}
@@ -2196,7 +2191,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
cpu_T[0], cpu_regs[reg]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
if (cc.mask != -1) {
tcg_temp_free(cc.reg);
@@ -2348,7 +2343,7 @@ static void gen_popa(DisasContext *s)
tcg_gen_addi_tl(cpu_A0, cpu_regs[R_ESP], i * size);
gen_lea_v_seg(s, s_ot, cpu_A0, R_SS, -1);
gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, 7 - i);
+ gen_op_mov_reg_v(d_ot, 7 - i, cpu_T[0]);
}
gen_stack_update(s, 8 * size);
@@ -3418,7 +3413,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
goto illegal_op;
#endif
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0xc4: /* pinsrw */
case 0x1c4:
@@ -3453,7 +3448,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
}
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
@@ -3604,7 +3599,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
cpu_T[0], tcg_const_i32(8 << ot));
ot = mo_64_32(s->dflag);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x1f0: /* crc32 or movbe */
@@ -3631,7 +3626,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if ((b & 1) == 0) {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, ot | MO_BE);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0,
s->mem_index, ot | MO_BE);
@@ -3647,7 +3642,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -3686,7 +3681,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_subi_tl(cpu_T[1], cpu_T[1], 1);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
}
@@ -3714,7 +3709,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_movi_tl(cpu_A0, -1);
tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T[1]);
tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
@@ -3888,7 +3883,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x0f3:
@@ -3907,7 +3902,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 1: /* blsr By,Ey */
tcg_gen_neg_tl(cpu_T[1], cpu_T[0]);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(ot, s->vex_v);
+ gen_op_mov_reg_v(ot, s->vex_v, cpu_T[0]);
gen_op_update2_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
@@ -3968,7 +3963,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
@@ -3978,7 +3973,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_W(val & 7)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_LEUW);
@@ -4015,7 +4010,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_LEUL);
@@ -4148,7 +4143,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, b & 31);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
default:
@@ -4473,7 +4468,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
tcg_gen_movi_tl(cpu_T[0], 0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
} else {
opreg = rm;
@@ -4587,7 +4582,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
break;
case 3: /* neg */
@@ -4595,7 +4590,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
gen_op_update_neg_cc();
set_cc_op(s, CC_OP_SUBB + ot);
@@ -4608,7 +4603,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
set_cc_op(s, CC_OP_MULB);
@@ -4619,10 +4614,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
@@ -4657,7 +4652,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
@@ -4669,12 +4664,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
default:
@@ -4893,18 +4888,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case MO_64:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_64, R_EAX);
+ gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
break;
#endif
case MO_32:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_32, R_EAX);
+ gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
break;
case MO_16:
gen_op_mov_TN_reg(MO_8, 0, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
default:
tcg_abort();
@@ -4916,20 +4911,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case MO_64:
gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
- gen_op_mov_reg_T0(MO_64, R_EDX);
+ gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
break;
#endif
case MO_32:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
- gen_op_mov_reg_T0(MO_32, R_EDX);
+ gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
break;
case MO_16:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
break;
default:
tcg_abort();
@@ -4983,7 +4978,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
}
set_cc_op(s, CC_OP_MULB + ot);
@@ -5000,7 +4995,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(ot, 1, rm);
gen_op_addl_T0_T1();
gen_op_mov_reg_T1(ot, reg);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
@@ -5104,7 +5099,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
- gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
+ gen_op_mov_reg_v(ot, (b & 7) | REX_B(s), cpu_T[0]);
break;
case 0x60: /* pusha */
if (CODE64(s))
@@ -5134,7 +5129,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
/* NOTE: order is important too for MMU exceptions */
s->popl_esp_hack = 1 << ot;
@@ -5227,7 +5222,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
+ gen_op_mov_reg_v(ot, (modrm & 7) | REX_B(s), cpu_T[0]);
}
break;
case 0x8a:
@@ -5237,7 +5232,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x8e: /* mov seg, Gv */
modrm = cpu_ldub_code(env, s->pc++);
@@ -5307,11 +5302,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
}
}
break;
@@ -5355,7 +5350,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
@@ -5369,12 +5364,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(MO_8, R_EAX);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
+ gen_op_mov_reg_v(MO_8, (b & 7) | REX_B(s), cpu_T[0]);
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
@@ -5385,7 +5380,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->pc += 8;
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], tmp);
- gen_op_mov_reg_T0(MO_64, reg);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
@@ -5393,7 +5388,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
break;
@@ -5414,7 +5409,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
do_xchg_reg:
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
gen_op_mov_reg_T1(ot, reg);
} else {
gen_lea_modrm(env, s, modrm);
@@ -6017,7 +6012,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0:
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
default:
goto illegal_op;
@@ -6481,7 +6476,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
- gen_op_mov_reg_T0(MO_8, R_AH);
+ gen_op_mov_reg_v(MO_8, R_AH, cpu_T[0]);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
@@ -6588,7 +6583,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_movi_tl(cpu_cc_dst, 0);
@@ -6645,7 +6640,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[0], cpu_cc_dst, cpu_tmp0,
cpu_regs[reg], cpu_T[0]);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
/************************/
/* bcd */
@@ -6817,14 +6812,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (dflag == MO_64) {
gen_op_mov_TN_reg(MO_64, 0, reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_64, reg);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
gen_op_mov_TN_reg(MO_32, 0, reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_32, reg);
+ gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
}
break;
case 0xd6: /* salc */
@@ -6832,7 +6827,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_compute_eflags_c(s, cpu_T[0]);
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_8, R_EAX);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
@@ -7318,11 +7313,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* sign extend */
if (d_ot == MO_64)
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
}
} else
#endif
@@ -7460,7 +7455,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_eob(s);
} else {
gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
break;
default:
@@ -7497,7 +7492,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
}
break;
@@ -7632,7 +7627,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
set_cc_op(s, CC_OP_EFLAGS);
break;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 51/60] target-i386: Remove gen_op_mov_reg_T1
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (49 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 50/60] target-i386: Remove gen_op_mov_reg_T0 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 52/60] target-i386: Remove gen_op_addl_T0_T1 Richard Henderson
` (9 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace with its definition, via Coccinelle.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ff0c6a9..ba43678 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -366,11 +366,6 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
}
}
-static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
-{
- gen_op_mov_reg_v(ot, reg, cpu_T[1]);
-}
-
static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg)
{
gen_op_mov_reg_v(size, reg, cpu_A0);
@@ -4994,7 +4989,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
gen_op_addl_T0_T1();
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
@@ -5002,7 +4997,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
gen_op_addl_T0_T1();
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
gen_op_update2_cc();
set_cc_op(s, CC_OP_ADDB + ot);
@@ -5410,7 +5405,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
@@ -5421,7 +5416,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
break;
case 0xc4: /* les Gv */
@@ -5454,7 +5449,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
if (s->is_jmp) {
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -6162,7 +6157,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_io_start();
tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
- gen_op_mov_reg_T1(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@@ -6196,7 +6191,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_io_start();
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
- gen_op_mov_reg_T1(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 52/60] target-i386: Remove gen_op_addl_T0_T1
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (50 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 51/60] target-i386: Remove gen_op_mov_reg_T1 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 53/60] target-i386: Remove gen_op_mov_TN_reg Richard Henderson
` (8 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace with its definition, via Coccinelle.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ba43678..ab471b4 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -416,11 +416,6 @@ static void gen_add_A0_im(DisasContext *s, int val)
gen_op_addl_A0_im(val);
}
-static inline void gen_op_addl_T0_T1(void)
-{
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
static inline void gen_op_jmp_T0(void)
{
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
@@ -1292,7 +1287,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
set_cc_op(s1, CC_OP_SBBB + ot);
break;
case OP_ADDL:
- gen_op_addl_T0_T1();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_ADDB + ot);
@@ -4988,14 +4983,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
- gen_op_addl_T0_T1();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_op_addl_T0_T1();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 53/60] target-i386: Remove gen_op_mov_TN_reg
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (51 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 52/60] target-i386: Remove gen_op_addl_T0_T1 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 54/60] target-i386: Remove gen_op_mov_reg_A0 Richard Henderson
` (7 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace with its definition, via Coccinelle.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 111 +++++++++++++++++++++++-------------------------
1 file changed, 53 insertions(+), 58 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ab471b4..7f2c718 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -381,11 +381,6 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
}
}
-static inline void gen_op_mov_TN_reg(TCGMemOp ot, int t_index, int reg)
-{
- gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
-}
-
static inline void gen_op_movl_A0_reg(int reg)
{
tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
@@ -1088,7 +1083,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
static inline void gen_stos(DisasContext *s, TCGMemOp ot)
{
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
@@ -1265,7 +1260,7 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
{
if (d != OR_TMP0) {
- gen_op_mov_TN_reg(ot, 0, d);
+ gen_op_mov_v_reg(ot, cpu_T[0], d);
} else {
gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
@@ -1331,7 +1326,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
{
if (d != OR_TMP0) {
- gen_op_mov_TN_reg(ot, 0, d);
+ gen_op_mov_v_reg(ot, cpu_T[0], d);
} else {
gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
@@ -1401,7 +1396,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
@@ -1437,7 +1432,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
if (op1 == OR_TMP0)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
op2 &= mask;
if (op2 != 0) {
@@ -1485,7 +1480,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
@@ -1571,7 +1566,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
op2 &= mask;
@@ -1649,7 +1644,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
if (op1 == OR_TMP0)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
if (is_right) {
switch (ot) {
@@ -1705,7 +1700,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
count = tcg_temp_new();
@@ -1779,7 +1774,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
{
if (s != OR_TMP1)
- gen_op_mov_TN_reg(ot, 1, s);
+ gen_op_mov_v_reg(ot, cpu_T[1], s);
switch(op) {
case OP_ROL:
gen_rot_rm_T1(s1, ot, d, 0);
@@ -2057,10 +2052,10 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (mod == 3) {
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
if (reg != OR_TMP0)
gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
@@ -2068,7 +2063,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
gen_lea_modrm(env, s, modrm);
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
@@ -4008,7 +4003,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x20: /* pinsrb */
if (mod == 3) {
- gen_op_mov_TN_reg(MO_32, 0, rm);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
} else {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
@@ -4463,7 +4458,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
opreg = rm;
}
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
gen_op(s, op, ot, opreg);
break;
case 1: /* OP Gv, Ev */
@@ -4477,7 +4472,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
}
gen_op(s, op, ot, reg);
break;
@@ -4557,7 +4552,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
switch(op) {
@@ -4588,7 +4583,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 4: /* mul */
switch(ot) {
case MO_8:
- gen_op_mov_TN_reg(MO_8, 1, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4599,7 +4594,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 1, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4637,7 +4632,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 5: /* imul */
switch(ot) {
case MO_8:
- gen_op_mov_TN_reg(MO_8, 1, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4649,7 +4644,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 1, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
@@ -4766,7 +4761,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (op >= 2 && op != 3 && op != 5)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
switch(op) {
@@ -4856,7 +4851,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -4866,7 +4861,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
- gen_op_mov_TN_reg(ot, 0, OR_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[0], OR_EAX);
tcg_gen_movi_tl(cpu_T[1], val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
@@ -4876,18 +4871,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
break;
#endif
case MO_32:
- gen_op_mov_TN_reg(MO_16, 0, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_8, 0, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[0], R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
@@ -4899,19 +4894,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
- gen_op_mov_TN_reg(MO_64, 0, R_EAX);
+ gen_op_mov_v_reg(MO_64, cpu_T[0], R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
break;
#endif
case MO_32:
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 0, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
@@ -4938,7 +4933,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[1], val);
} else {
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
}
switch (ot) {
#ifdef TARGET_X86_64
@@ -4981,14 +4976,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
@@ -5082,7 +5077,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
- gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s));
+ gen_op_mov_v_reg(MO_32, cpu_T[0], (b & 7) | REX_B(s));
gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
@@ -5276,7 +5271,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
switch (s_ot) {
case MO_UB:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
@@ -5342,7 +5337,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(ot, 0, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[0], R_EAX);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
}
}
@@ -5397,13 +5392,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
do_xchg_reg:
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
@@ -5523,7 +5518,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
opreg = rm;
}
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
if (shift) {
TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++));
@@ -6164,7 +6159,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_TN_reg(ot, 1, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
if (use_icount)
gen_io_start();
@@ -6198,7 +6193,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_TN_reg(ot, 1, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
if (use_icount)
gen_io_start();
@@ -6454,7 +6449,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
- gen_op_mov_TN_reg(MO_8, 0, R_AH);
+ gen_op_mov_v_reg(MO_8, cpu_T[0], R_AH);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
@@ -6502,7 +6497,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
/* load shift */
val = cpu_ldub_code(env, s->pc++);
@@ -6528,7 +6523,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(MO_32, 1, reg);
+ gen_op_mov_v_reg(MO_32, cpu_T[1], reg);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
/* specific case: we need to add a displacement */
@@ -6538,7 +6533,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
bt_op:
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
@@ -6786,7 +6781,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_lea_modrm(env, s, modrm);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -6800,13 +6795,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == MO_64) {
- gen_op_mov_TN_reg(MO_64, 0, reg);
+ gen_op_mov_v_reg(MO_64, cpu_T[0], reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
- gen_op_mov_TN_reg(MO_32, 0, reg);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
@@ -7299,7 +7294,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(MO_32, 0, rm);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
/* sign extend */
if (d_ot == MO_64)
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
@@ -7438,7 +7433,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
@@ -7475,7 +7470,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
if (b & 2) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 54/60] target-i386: Remove gen_op_mov_reg_A0
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (52 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 53/60] target-i386: Remove gen_op_mov_TN_reg Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 55/60] target-i386: Remove gen_op_movl_A0_reg Richard Henderson
` (6 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Replace with its definition.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7f2c718..62a2cbc 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -366,11 +366,6 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
}
}
-static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg)
-{
- gen_op_mov_reg_v(size, reg, cpu_A0);
-}
-
static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
{
if (ot == MO_8 && byte_reg_is_xH(reg)) {
@@ -5309,7 +5304,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->addseg = 0;
gen_lea_modrm(env, s, modrm);
s->addseg = val;
- gen_op_mov_reg_A0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_A0);
break;
case 0xa0: /* mov EAX, Ov */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 55/60] target-i386: Remove gen_op_movl_A0_reg
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (53 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 54/60] target-i386: Remove gen_op_mov_reg_A0 Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im Richard Henderson
` (5 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
No longer used.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 62a2cbc..19cabf6 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -376,11 +376,6 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
}
}
-static inline void gen_op_movl_A0_reg(int reg)
-{
- tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
-}
-
static inline void gen_op_addl_A0_im(int32_t val)
{
tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (54 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 55/60] target-i386: Remove gen_op_movl_A0_reg Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-12-26 18:58 ` Peter Maydell
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 57/60] target-i386: Tidy some size computation Richard Henderson
` (4 subsequent siblings)
60 siblings, 1 reply; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im
and clean up the ifdef.
Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 27 +++++----------------------
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 19cabf6..ee9d586 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -376,29 +376,12 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
}
}
-static inline void gen_op_addl_A0_im(int32_t val)
-{
- tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
-#ifdef TARGET_X86_64
- tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
-#endif
-}
-
-#ifdef TARGET_X86_64
-static inline void gen_op_addq_A0_im(int64_t val)
-{
- tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
-}
-#endif
-
static void gen_add_A0_im(DisasContext *s, int val)
{
-#ifdef TARGET_X86_64
- if (CODE64(s))
- gen_op_addq_A0_im(val);
- else
-#endif
- gen_op_addl_A0_im(val);
+ tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
+ if (!CODE64(s)) {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
+ }
}
static inline void gen_op_jmp_T0(void)
@@ -6231,7 +6214,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
exception */
gen_op_jmp_T0();
/* pop selector */
- gen_op_addl_A0_im(1 << dflag);
+ gen_add_A0_im(s, 1 << dflag);
gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im Richard Henderson
@ 2013-12-26 18:58 ` Peter Maydell
2013-12-26 19:10 ` Richard Henderson
0 siblings, 1 reply; 75+ messages in thread
From: Peter Maydell @ 2013-12-26 18:58 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 29 November 2013 03:00, Richard Henderson <rth@twiddle.net> wrote:
> Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im
> and clean up the ifdef.
>
> Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-i386/translate.c | 27 +++++----------------------
> 1 file changed, 5 insertions(+), 22 deletions(-)
>
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index 19cabf6..ee9d586 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -376,29 +376,12 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
> }
> }
>
> -static inline void gen_op_addl_A0_im(int32_t val)
> -{
> - tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
> -#ifdef TARGET_X86_64
> - tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
> -#endif
> -}
> -
> -#ifdef TARGET_X86_64
> -static inline void gen_op_addq_A0_im(int64_t val)
> -{
> - tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
> -}
> -#endif
> -
> static void gen_add_A0_im(DisasContext *s, int val)
> {
> -#ifdef TARGET_X86_64
> - if (CODE64(s))
> - gen_op_addq_A0_im(val);
> - else
> -#endif
> - gen_op_addl_A0_im(val);
> + tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
> + if (!CODE64(s)) {
> + tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
> + }
> }
>
> static inline void gen_op_jmp_T0(void)
> @@ -6231,7 +6214,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
> exception */
> gen_op_jmp_T0();
> /* pop selector */
> - gen_op_addl_A0_im(1 << dflag);
> + gen_add_A0_im(s, 1 << dflag);
Why is it OK that we no longer zero extend the result of
the add from 32 to 64 bits if CODE64(s) ? Previously we
did the extend unconditionally.
> gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
> gen_op_movl_seg_T0_vm(R_CS);
> /* add stack offset */
thanks
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im
2013-12-26 18:58 ` Peter Maydell
@ 2013-12-26 19:10 ` Richard Henderson
2013-12-26 22:34 ` Peter Maydell
0 siblings, 1 reply; 75+ messages in thread
From: Richard Henderson @ 2013-12-26 19:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 12/26/2013 10:58 AM, Peter Maydell wrote:
> On 29 November 2013 03:00, Richard Henderson <rth@twiddle.net> wrote:
>> Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im
>> and clean up the ifdef.
>>
>> Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im.
>>
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> ---
>> target-i386/translate.c | 27 +++++----------------------
>> 1 file changed, 5 insertions(+), 22 deletions(-)
>>
>> diff --git a/target-i386/translate.c b/target-i386/translate.c
>> index 19cabf6..ee9d586 100644
>> --- a/target-i386/translate.c
>> +++ b/target-i386/translate.c
>> @@ -376,29 +376,12 @@ static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
>> }
>> }
>>
>> -static inline void gen_op_addl_A0_im(int32_t val)
>> -{
>> - tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
>> -#ifdef TARGET_X86_64
>> - tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
>> -#endif
>> -}
>> -
>> -#ifdef TARGET_X86_64
>> -static inline void gen_op_addq_A0_im(int64_t val)
>> -{
>> - tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
>> -}
>> -#endif
>> -
>> static void gen_add_A0_im(DisasContext *s, int val)
>> {
>> -#ifdef TARGET_X86_64
>> - if (CODE64(s))
>> - gen_op_addq_A0_im(val);
>> - else
>> -#endif
>> - gen_op_addl_A0_im(val);
>> + tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
>> + if (!CODE64(s)) {
>> + tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
>> + }
>> }
>>
>> static inline void gen_op_jmp_T0(void)
>> @@ -6231,7 +6214,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
>> exception */
>> gen_op_jmp_T0();
>> /* pop selector */
>> - gen_op_addl_A0_im(1 << dflag);
>> + gen_add_A0_im(s, 1 << dflag);
>
> Why is it OK that we no longer zero extend the result of
> the add from 32 to 64 bits if CODE64(s) ? Previously we
> did the extend unconditionally.
I can only imagine that's a bug, to have suddenly zapped the high 32-bits of
the address from which we're loading. Indeed, even this is probably not 100%
correct wrt stack segment wraparound.
Probably better to generate both addresses from ESP and ESP+C from scratch,
using gen_lea_v_seg.
r~
r~
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im
2013-12-26 19:10 ` Richard Henderson
@ 2013-12-26 22:34 ` Peter Maydell
2013-12-27 15:17 ` Richard Henderson
0 siblings, 1 reply; 75+ messages in thread
From: Peter Maydell @ 2013-12-26 22:34 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 26 December 2013 19:10, Richard Henderson <rth@twiddle.net> wrote:
> On 12/26/2013 10:58 AM, Peter Maydell wrote:
>>> @@ -6231,7 +6214,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
>>> exception */
>>> gen_op_jmp_T0();
>>> /* pop selector */
>>> - gen_op_addl_A0_im(1 << dflag);
>>> + gen_add_A0_im(s, 1 << dflag);
>>
>> Why is it OK that we no longer zero extend the result of
>> the add from 32 to 64 bits if CODE64(s) ? Previously we
>> did the extend unconditionally.
>
> I can only imagine that's a bug, to have suddenly zapped the high 32-bits of
> the address from which we're loading. Indeed, even this is probably not 100%
> correct wrt stack segment wraparound.
Looking a bit more closely, is it even possible for code64 to be
1 if we're in real or vm86 mode? If not, then the behaviour here
is unchanged (ie still always zero extends).
> Probably better to generate both addresses from ESP and ESP+C from scratch,
> using gen_lea_v_seg.
Agreed (compare gen_popa which does get the multiple-pops
behaviour right I think).
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im
2013-12-26 22:34 ` Peter Maydell
@ 2013-12-27 15:17 ` Richard Henderson
2013-12-27 15:32 ` Peter Maydell
0 siblings, 1 reply; 75+ messages in thread
From: Richard Henderson @ 2013-12-27 15:17 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 12/26/2013 02:34 PM, Peter Maydell wrote:
> Looking a bit more closely, is it even possible for code64 to be
> 1 if we're in real or vm86 mode? If not, then the behaviour here
> is unchanged (ie still always zero extends).
No, real or vm86 mode implies 16-bit.
r~
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im
2013-12-27 15:17 ` Richard Henderson
@ 2013-12-27 15:32 ` Peter Maydell
0 siblings, 0 replies; 75+ messages in thread
From: Peter Maydell @ 2013-12-27 15:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 27 December 2013 15:17, Richard Henderson <rth@twiddle.net> wrote:
> On 12/26/2013 02:34 PM, Peter Maydell wrote:
>> Looking a bit more closely, is it even possible for code64 to be
>> 1 if we're in real or vm86 mode? If not, then the behaviour here
>> is unchanged (ie still always zero extends).
>
> No, real or vm86 mode implies 16-bit.
In that case
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
since that means this patch isn't changing anything (though
as you say the zero-extend is probably strictly speaking a
bug).
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread
* [Qemu-devel] [PATCH v2 57/60] target-i386: Tidy some size computation
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (55 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 58/60] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v Richard Henderson
` (3 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Clean up relics of multiple size domains: - MO_16 + 1 => - 1 + 1 => 0.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ee9d586..9052907 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4765,7 +4765,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 3: /* lcall Ev */
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_lcall:
if (s->pe && !s->vm86) {
@@ -4792,7 +4792,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 5: /* ljmp Ev */
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_ljmp:
if (s->pe && !s->vm86) {
@@ -5407,7 +5407,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
/* load the segment first to handle exceptions properly */
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 58/60] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (56 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 57/60] target-i386: Tidy some size computation Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 59/60] target-i386: Tidy ljmp Richard Henderson
` (2 subsequent siblings)
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
And make the destination argument explicit.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9052907..fcf4c67 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -384,9 +384,9 @@ static void gen_add_A0_im(DisasContext *s, int val)
}
}
-static inline void gen_op_jmp_T0(void)
+static inline void gen_op_jmp_v(TCGv dest)
{
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
+ tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip));
}
static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val)
@@ -423,7 +423,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
static inline void gen_jmp_im(target_ulong pc)
{
tcg_gen_movi_tl(cpu_tmp0, pc);
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
+ gen_op_jmp_v(cpu_tmp0);
}
/* Compute SEG:REG into A0. SEG is selected from the override segment
@@ -4760,7 +4760,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
next_eip = s->pc - s->cs_base;
tcg_gen_movi_tl(cpu_T[1], next_eip);
gen_push_v(s, cpu_T[1]);
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 3: /* lcall Ev */
@@ -4787,7 +4787,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 5: /* ljmp Ev */
@@ -4804,7 +4804,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_op_movl_seg_T0_vm(R_CS);
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
}
gen_eob(s);
break;
@@ -6187,14 +6187,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = gen_pop_T0(s);
gen_stack_update(s, val + (1 << ot));
/* Note that gen_pop_T0 uses a zero-extending load. */
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 0xc3: /* ret */
ot = gen_pop_T0(s);
gen_pop_update(s, ot);
/* Note that gen_pop_T0 uses a zero-extending load. */
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 0xca: /* lret im */
@@ -6212,7 +6212,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
/* pop selector */
gen_add_A0_im(s, 1 << dflag);
gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 59/60] target-i386: Tidy ljmp
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (57 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 58/60] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 60/60] target-i386: Deconstruct the cpu_T array Richard Henderson
2013-12-23 20:15 ` [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
Remove an unnecessary move opcode.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index fcf4c67..1a52c51 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4803,8 +4803,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_const_i32(s->pc - pc_start));
} else {
gen_op_movl_seg_T0_vm(R_CS);
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
- gen_op_jmp_v(cpu_T[0]);
+ gen_op_jmp_v(cpu_T[1]);
}
gen_eob(s);
break;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* [Qemu-devel] [PATCH v2 60/60] target-i386: Deconstruct the cpu_T array
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (58 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 59/60] target-i386: Tidy ljmp Richard Henderson
@ 2013-11-29 3:00 ` Richard Henderson
2013-12-23 20:15 ` [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
60 siblings, 0 replies; 75+ messages in thread
From: Richard Henderson @ 2013-11-29 3:00 UTC (permalink / raw)
To: qemu-devel
All references to cpu_T are done with a constant index. It aids
readability to decompose the array into two scalar variables.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 1257 ++++++++++++++++++++++++-----------------------
1 file changed, 646 insertions(+), 611 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 1a52c51..b09b7f7 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -68,7 +68,7 @@ static TCGv cpu_regs[CPU_NB_REGS];
static TCGv_i32 cpu_seg_sel[6];
static TCGv cpu_seg_base[6];
/* local temps */
-static TCGv cpu_T[2];
+static TCGv cpu_T0, cpu_T1;
/* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0, cpu_tmp4;
static TCGv_ptr cpu_ptr0, cpu_ptr1;
@@ -397,7 +397,7 @@ static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val)
static inline void gen_op_add_reg_T0(TCGMemOp size, int reg)
{
- tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
+ tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T0);
gen_op_mov_reg_v(size, reg, cpu_tmp0);
}
@@ -414,9 +414,9 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
{
if (d == OR_TMP0) {
- gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, idx, cpu_T0, cpu_A0);
} else {
- gen_op_mov_reg_v(idx, d, cpu_T[0]);
+ gen_op_mov_reg_v(idx, d, cpu_T0);
}
}
@@ -494,8 +494,8 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)
static inline void gen_op_movl_T0_Dshift(TCGMemOp ot)
{
- tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
- tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
+ tcg_gen_ld32s_tl(cpu_T0, cpu_env, offsetof(CPUX86State, df));
+ tcg_gen_shli_tl(cpu_T0, cpu_T0, ot);
};
static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)
@@ -598,7 +598,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
gen_update_cc_op(s);
gen_jmp_im(cur_eip);
state_saved = 1;
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
switch (ot) {
case MO_8:
gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
@@ -620,7 +620,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
}
svm_flags |= (1 << (4 + ot));
next_eip = s->pc - s->cs_base;
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32,
tcg_const_i32(svm_flags),
tcg_const_i32(next_eip - cur_eip));
@@ -630,9 +630,9 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
static inline void gen_movs(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
gen_string_movl_A0_EDI(s);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -640,31 +640,31 @@ static inline void gen_movs(DisasContext *s, TCGMemOp ot)
static void gen_op_update1_cc(void)
{
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
}
static void gen_op_update2_cc(void)
{
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T1);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
}
static void gen_op_update3_cc(TCGv reg)
{
tcg_gen_mov_tl(cpu_cc_src2, reg);
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T1);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
}
static inline void gen_op_testl_T0_T1_cc(void)
{
- tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
+ tcg_gen_and_tl(cpu_cc_dst, cpu_T0, cpu_T1);
}
static void gen_op_update_neg_cc(void)
{
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
+ tcg_gen_neg_tl(cpu_cc_src, cpu_T0);
tcg_gen_movi_tl(cpu_cc_srcT, 0);
}
@@ -1006,11 +1006,11 @@ static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg)
value 'b'. In the fast case, T0 is guaranted not to be used. */
static inline void gen_jcc1_noeob(DisasContext *s, int b, int l1)
{
- CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]);
+ CCPrepare cc = gen_prepare_cc(s, b, cpu_T0);
if (cc.mask != -1) {
- tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask);
- cc.reg = cpu_T[0];
+ tcg_gen_andi_tl(cpu_T0, cc.reg, cc.mask);
+ cc.reg = cpu_T0;
}
if (cc.use_reg2) {
tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1);
@@ -1024,12 +1024,12 @@ static inline void gen_jcc1_noeob(DisasContext *s, int b, int l1)
A translation block must end soon. */
static inline void gen_jcc1(DisasContext *s, int b, int l1)
{
- CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]);
+ CCPrepare cc = gen_prepare_cc(s, b, cpu_T0);
gen_update_cc_op(s);
if (cc.mask != -1) {
- tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask);
- cc.reg = cpu_T[0];
+ tcg_gen_andi_tl(cpu_T0, cc.reg, cc.mask);
+ cc.reg = cpu_T0;
}
set_cc_op(s, CC_OP_DYNAMIC);
if (cc.use_reg2) {
@@ -1056,9 +1056,9 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
static inline void gen_stos(DisasContext *s, TCGMemOp ot)
{
- gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T0, R_EAX);
gen_string_movl_A0_EDI(s);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
@@ -1066,8 +1066,8 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot)
static inline void gen_lods(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
}
@@ -1075,7 +1075,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
static inline void gen_scas(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
gen_op(s, OP_CMPL, ot, R_EAX);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
@@ -1084,7 +1084,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot)
static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_EDI(s);
- gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
gen_string_movl_A0_ESI(s);
gen_op(s, OP_CMPL, ot, OR_TMP0);
gen_op_movl_T0_Dshift(ot);
@@ -1099,12 +1099,12 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_string_movl_A0_EDI(s);
/* Note: we must do this dummy write first to be restartable in
case of page fault. */
- tcg_gen_movi_tl(cpu_T[0], 0);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ tcg_gen_movi_tl(cpu_T0, 0);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
- gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_helper_in_func(ot, cpu_T0, cpu_tmp2_i32);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
if (use_icount)
@@ -1116,11 +1116,11 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
if (use_icount)
gen_io_start();
gen_string_movl_A0_ESI(s);
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[R_EDX]);
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
- tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T0);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
gen_op_movl_T0_Dshift(ot);
@@ -1233,63 +1233,63 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
{
if (d != OR_TMP0) {
- gen_op_mov_v_reg(ot, cpu_T[0], d);
+ gen_op_mov_v_reg(ot, cpu_T0, d);
} else {
- gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s1, ot, cpu_T0, cpu_A0);
}
switch(op) {
case OP_ADCL:
gen_compute_eflags_c(s1, cpu_tmp4);
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
+ tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1);
+ tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_tmp4);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_ADCB + ot);
break;
case OP_SBBL:
gen_compute_eflags_c(s1, cpu_tmp4);
- tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
+ tcg_gen_sub_tl(cpu_T0, cpu_T0, cpu_T1);
+ tcg_gen_sub_tl(cpu_T0, cpu_T0, cpu_tmp4);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update3_cc(cpu_tmp4);
set_cc_op(s1, CC_OP_SBBB + ot);
break;
case OP_ADDL:
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_ADDB + ot);
break;
case OP_SUBL:
- tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]);
- tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_mov_tl(cpu_cc_srcT, cpu_T0);
+ tcg_gen_sub_tl(cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_SUBB + ot);
break;
default:
case OP_ANDL:
- tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
case OP_ORL:
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_or_tl(cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
case OP_XORL:
- tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_T1);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update1_cc();
set_cc_op(s1, CC_OP_LOGICB + ot);
break;
case OP_CMPL:
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
- tcg_gen_mov_tl(cpu_cc_srcT, cpu_T[0]);
- tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T1);
+ tcg_gen_mov_tl(cpu_cc_srcT, cpu_T0);
+ tcg_gen_sub_tl(cpu_cc_dst, cpu_T0, cpu_T1);
set_cc_op(s1, CC_OP_SUBB + ot);
break;
}
@@ -1299,20 +1299,20 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
{
if (d != OR_TMP0) {
- gen_op_mov_v_reg(ot, cpu_T[0], d);
+ gen_op_mov_v_reg(ot, cpu_T0, d);
} else {
- gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s1, ot, cpu_T0, cpu_A0);
}
gen_compute_eflags_c(s1, cpu_cc_src);
if (c > 0) {
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
+ tcg_gen_addi_tl(cpu_T0, cpu_T0, 1);
set_cc_op(s1, CC_OP_INCB + ot);
} else {
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
+ tcg_gen_addi_tl(cpu_T0, cpu_T0, -1);
set_cc_op(s1, CC_OP_DECB + ot);
}
gen_op_st_rm_T0_A0(s1, ot, d);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
}
static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,
@@ -1367,33 +1367,33 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], op1);
+ gen_op_mov_v_reg(ot, cpu_T0, op1);
}
- tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
- tcg_gen_subi_tl(cpu_tmp0, cpu_T[1], 1);
+ tcg_gen_andi_tl(cpu_T1, cpu_T1, mask);
+ tcg_gen_subi_tl(cpu_tmp0, cpu_T1, 1);
if (is_right) {
if (is_arith) {
- gen_exts(ot, cpu_T[0]);
- tcg_gen_sar_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
- tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_exts(ot, cpu_T0);
+ tcg_gen_sar_tl(cpu_tmp0, cpu_T0, cpu_tmp0);
+ tcg_gen_sar_tl(cpu_T0, cpu_T0, cpu_T1);
} else {
- gen_extu(ot, cpu_T[0]);
- tcg_gen_shr_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
- tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_extu(ot, cpu_T0);
+ tcg_gen_shr_tl(cpu_tmp0, cpu_T0, cpu_tmp0);
+ tcg_gen_shr_tl(cpu_T0, cpu_T0, cpu_T1);
}
} else {
- tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
- tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_shl_tl(cpu_tmp0, cpu_T0, cpu_tmp0);
+ tcg_gen_shl_tl(cpu_T0, cpu_T0, cpu_T1);
}
/* store */
gen_op_st_rm_T0_A0(s, ot, op1);
- gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, cpu_T[1], is_right);
+ gen_shift_flags(s, ot, cpu_T0, cpu_tmp0, cpu_T1, is_right);
}
static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
@@ -1403,25 +1403,25 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
else
- gen_op_mov_v_reg(ot, cpu_T[0], op1);
+ gen_op_mov_v_reg(ot, cpu_T0, op1);
op2 &= mask;
if (op2 != 0) {
if (is_right) {
if (is_arith) {
- gen_exts(ot, cpu_T[0]);
- tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
- tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
+ gen_exts(ot, cpu_T0);
+ tcg_gen_sari_tl(cpu_tmp4, cpu_T0, op2 - 1);
+ tcg_gen_sari_tl(cpu_T0, cpu_T0, op2);
} else {
- gen_extu(ot, cpu_T[0]);
- tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
- tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
+ gen_extu(ot, cpu_T0);
+ tcg_gen_shri_tl(cpu_tmp4, cpu_T0, op2 - 1);
+ tcg_gen_shri_tl(cpu_T0, cpu_T0, op2);
}
} else {
- tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
- tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
+ tcg_gen_shli_tl(cpu_tmp4, cpu_T0, op2 - 1);
+ tcg_gen_shli_tl(cpu_T0, cpu_T0, op2);
}
}
@@ -1431,7 +1431,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
/* update eflags if non zero shift */
if (op2 != 0) {
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot);
}
}
@@ -1451,41 +1451,41 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], op1);
+ gen_op_mov_v_reg(ot, cpu_T0, op1);
}
- tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
+ tcg_gen_andi_tl(cpu_T1, cpu_T1, mask);
switch (ot) {
case MO_8:
/* Replicate the 8-bit input so that a 32-bit rotate works. */
- tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_muli_tl(cpu_T[0], cpu_T[0], 0x01010101);
+ tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
+ tcg_gen_muli_tl(cpu_T0, cpu_T0, 0x01010101);
goto do_long;
case MO_16:
/* Replicate the 16-bit input so that a 32-bit rotate works. */
- tcg_gen_deposit_tl(cpu_T[0], cpu_T[0], cpu_T[0], 16, 16);
+ tcg_gen_deposit_tl(cpu_T0, cpu_T0, cpu_T0, 16, 16);
goto do_long;
do_long:
#ifdef TARGET_X86_64
case MO_32:
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
if (is_right) {
tcg_gen_rotr_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
} else {
tcg_gen_rotl_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
}
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
+ tcg_gen_extu_i32_tl(cpu_T0, cpu_tmp2_i32);
break;
#endif
default:
if (is_right) {
- tcg_gen_rotr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_rotr_tl(cpu_T0, cpu_T0, cpu_T1);
} else {
- tcg_gen_rotl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_rotl_tl(cpu_T0, cpu_T0, cpu_T1);
}
break;
}
@@ -1501,12 +1501,12 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
since we've computed the flags into CC_SRC, these variables are
currently dead. */
if (is_right) {
- tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
- tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
+ tcg_gen_shri_tl(cpu_cc_src2, cpu_T0, mask - 1);
+ tcg_gen_shri_tl(cpu_cc_dst, cpu_T0, mask);
tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
} else {
- tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
- tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
+ tcg_gen_shri_tl(cpu_cc_src2, cpu_T0, mask);
+ tcg_gen_andi_tl(cpu_cc_dst, cpu_T0, 1);
}
tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1);
tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst);
@@ -1517,7 +1517,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)
exactly as we computed above. */
t0 = tcg_const_i32(0);
t1 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t1, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(t1, cpu_T1);
tcg_gen_movi_i32(cpu_tmp2_i32, CC_OP_ADCOX);
tcg_gen_movi_i32(cpu_tmp3_i32, CC_OP_EFLAGS);
tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0,
@@ -1537,9 +1537,9 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], op1);
+ gen_op_mov_v_reg(ot, cpu_T0, op1);
}
op2 &= mask;
@@ -1547,20 +1547,20 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
switch (ot) {
#ifdef TARGET_X86_64
case MO_32:
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
if (is_right) {
tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2);
} else {
tcg_gen_rotli_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2);
}
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
+ tcg_gen_extu_i32_tl(cpu_T0, cpu_tmp2_i32);
break;
#endif
default:
if (is_right) {
- tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], op2);
+ tcg_gen_rotri_tl(cpu_T0, cpu_T0, op2);
} else {
- tcg_gen_rotli_tl(cpu_T[0], cpu_T[0], op2);
+ tcg_gen_rotli_tl(cpu_T0, cpu_T0, op2);
}
break;
case MO_8:
@@ -1573,10 +1573,10 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
if (is_right) {
shift = mask + 1 - shift;
}
- gen_extu(ot, cpu_T[0]);
- tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], shift);
- tcg_gen_shri_tl(cpu_T[0], cpu_T[0], mask + 1 - shift);
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
+ gen_extu(ot, cpu_T0);
+ tcg_gen_shli_tl(cpu_tmp0, cpu_T0, shift);
+ tcg_gen_shri_tl(cpu_T0, cpu_T0, mask + 1 - shift);
+ tcg_gen_or_tl(cpu_T0, cpu_T0, cpu_tmp0);
break;
}
}
@@ -1593,12 +1593,12 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
since we've computed the flags into CC_SRC, these variables are
currently dead. */
if (is_right) {
- tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
- tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
+ tcg_gen_shri_tl(cpu_cc_src2, cpu_T0, mask - 1);
+ tcg_gen_shri_tl(cpu_cc_dst, cpu_T0, mask);
tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
} else {
- tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
- tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
+ tcg_gen_shri_tl(cpu_cc_src2, cpu_T0, mask);
+ tcg_gen_andi_tl(cpu_cc_dst, cpu_T0, 1);
}
tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1);
tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst);
@@ -1615,24 +1615,24 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
/* load */
if (op1 == OR_TMP0)
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
else
- gen_op_mov_v_reg(ot, cpu_T[0], op1);
+ gen_op_mov_v_reg(ot, cpu_T0, op1);
if (is_right) {
switch (ot) {
case MO_8:
- gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
+ gen_helper_rcrb(cpu_T0, cpu_env, cpu_T0, cpu_T1);
break;
case MO_16:
- gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
+ gen_helper_rcrw(cpu_T0, cpu_env, cpu_T0, cpu_T1);
break;
case MO_32:
- gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
+ gen_helper_rcrl(cpu_T0, cpu_env, cpu_T0, cpu_T1);
break;
#ifdef TARGET_X86_64
case MO_64:
- gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
+ gen_helper_rcrq(cpu_T0, cpu_env, cpu_T0, cpu_T1);
break;
#endif
default:
@@ -1641,17 +1641,17 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
} else {
switch (ot) {
case MO_8:
- gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
+ gen_helper_rclb(cpu_T0, cpu_env, cpu_T0, cpu_T1);
break;
case MO_16:
- gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
+ gen_helper_rclw(cpu_T0, cpu_env, cpu_T0, cpu_T1);
break;
case MO_32:
- gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
+ gen_helper_rcll(cpu_T0, cpu_env, cpu_T0, cpu_T1);
break;
#ifdef TARGET_X86_64
case MO_64:
- gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
+ gen_helper_rclq(cpu_T0, cpu_env, cpu_T0, cpu_T1);
break;
#endif
default:
@@ -1671,9 +1671,9 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
/* load */
if (op1 == OR_TMP0) {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], op1);
+ gen_op_mov_v_reg(ot, cpu_T0, op1);
}
count = tcg_temp_new();
@@ -1685,11 +1685,11 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
portion by constructing it as a 32-bit value. */
if (is_right) {
- tcg_gen_deposit_tl(cpu_tmp0, cpu_T[0], cpu_T[1], 16, 16);
- tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
- tcg_gen_mov_tl(cpu_T[0], cpu_tmp0);
+ tcg_gen_deposit_tl(cpu_tmp0, cpu_T0, cpu_T1, 16, 16);
+ tcg_gen_mov_tl(cpu_T1, cpu_T0);
+ tcg_gen_mov_tl(cpu_T0, cpu_tmp0);
} else {
- tcg_gen_deposit_tl(cpu_T[1], cpu_T[0], cpu_T[1], 16, 16);
+ tcg_gen_deposit_tl(cpu_T1, cpu_T0, cpu_T1, 16, 16);
}
/* FALLTHRU */
#ifdef TARGET_X86_64
@@ -1697,57 +1697,57 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
/* Concatenate the two 32-bit values and use a 64-bit shift. */
tcg_gen_subi_tl(cpu_tmp0, count, 1);
if (is_right) {
- tcg_gen_concat_tl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_shr_i64(cpu_tmp0, cpu_T[0], cpu_tmp0);
- tcg_gen_shr_i64(cpu_T[0], cpu_T[0], count);
+ tcg_gen_concat_tl_i64(cpu_T0, cpu_T0, cpu_T1);
+ tcg_gen_shr_i64(cpu_tmp0, cpu_T0, cpu_tmp0);
+ tcg_gen_shr_i64(cpu_T0, cpu_T0, count);
} else {
- tcg_gen_concat_tl_i64(cpu_T[0], cpu_T[1], cpu_T[0]);
- tcg_gen_shl_i64(cpu_tmp0, cpu_T[0], cpu_tmp0);
- tcg_gen_shl_i64(cpu_T[0], cpu_T[0], count);
+ tcg_gen_concat_tl_i64(cpu_T0, cpu_T1, cpu_T0);
+ tcg_gen_shl_i64(cpu_tmp0, cpu_T0, cpu_tmp0);
+ tcg_gen_shl_i64(cpu_T0, cpu_T0, count);
tcg_gen_shri_i64(cpu_tmp0, cpu_tmp0, 32);
- tcg_gen_shri_i64(cpu_T[0], cpu_T[0], 32);
+ tcg_gen_shri_i64(cpu_T0, cpu_T0, 32);
}
break;
#endif
default:
tcg_gen_subi_tl(cpu_tmp0, count, 1);
if (is_right) {
- tcg_gen_shr_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
+ tcg_gen_shr_tl(cpu_tmp0, cpu_T0, cpu_tmp0);
tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count);
- tcg_gen_shr_tl(cpu_T[0], cpu_T[0], count);
- tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp4);
+ tcg_gen_shr_tl(cpu_T0, cpu_T0, count);
+ tcg_gen_shl_tl(cpu_T1, cpu_T1, cpu_tmp4);
} else {
- tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp0);
+ tcg_gen_shl_tl(cpu_tmp0, cpu_T0, cpu_tmp0);
if (ot == MO_16) {
/* Only needed if count > 16, for Intel behaviour. */
tcg_gen_subfi_tl(cpu_tmp4, 33, count);
- tcg_gen_shr_tl(cpu_tmp4, cpu_T[1], cpu_tmp4);
+ tcg_gen_shr_tl(cpu_tmp4, cpu_T1, cpu_tmp4);
tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, cpu_tmp4);
}
tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count);
- tcg_gen_shl_tl(cpu_T[0], cpu_T[0], count);
- tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp4);
+ tcg_gen_shl_tl(cpu_T0, cpu_T0, count);
+ tcg_gen_shr_tl(cpu_T1, cpu_T1, cpu_tmp4);
}
tcg_gen_movi_tl(cpu_tmp4, 0);
- tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[1], count, cpu_tmp4,
- cpu_tmp4, cpu_T[1]);
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T1, count, cpu_tmp4,
+ cpu_tmp4, cpu_T1);
+ tcg_gen_or_tl(cpu_T0, cpu_T0, cpu_T1);
break;
}
/* store */
gen_op_st_rm_T0_A0(s, ot, op1);
- gen_shift_flags(s, ot, cpu_T[0], cpu_tmp0, count, is_right);
+ gen_shift_flags(s, ot, cpu_T0, cpu_tmp0, count, is_right);
tcg_temp_free(count);
}
static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
{
if (s != OR_TMP1)
- gen_op_mov_v_reg(ot, cpu_T[1], s);
+ gen_op_mov_v_reg(ot, cpu_T1, s);
switch(op) {
case OP_ROL:
gen_rot_rm_T1(s1, ot, d, 0);
@@ -1795,7 +1795,7 @@ static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c)
break;
default:
/* currently not optimized */
- tcg_gen_movi_tl(cpu_T[1], c);
+ tcg_gen_movi_tl(cpu_T1, c);
gen_shift(s1, op, ot, d, OR_TMP1);
break;
}
@@ -2025,23 +2025,23 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
if (mod == 3) {
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_v_reg(ot, cpu_T[0], reg);
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_v_reg(ot, cpu_T0, reg);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], rm);
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
if (reg != OR_TMP0)
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
}
} else {
gen_lea_modrm(env, s, modrm);
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_v_reg(ot, cpu_T[0], reg);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_mov_v_reg(ot, cpu_T0, reg);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
if (reg != OR_TMP0)
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
}
}
}
@@ -2137,7 +2137,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- cc = gen_prepare_cc(s, b, cpu_T[1]);
+ cc = gen_prepare_cc(s, b, cpu_T1);
if (cc.mask != -1) {
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cc.reg, cc.mask);
@@ -2147,9 +2147,9 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
cc.reg2 = tcg_const_tl(cc.imm);
}
- tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
- cpu_T[0], cpu_regs[reg]);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ tcg_gen_movcond_tl(cc.cond, cpu_T0, cc.reg, cc.reg2,
+ cpu_T0, cpu_regs[reg]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
if (cc.mask != -1) {
tcg_temp_free(cc.reg);
@@ -2161,14 +2161,14 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,
static inline void gen_op_movl_T0_seg(int seg_reg)
{
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_seg_sel[seg_reg]);
+ tcg_gen_extu_i32_tl(cpu_T0, cpu_seg_sel[seg_reg]);
}
static inline void gen_op_movl_seg_T0_vm(int seg_reg)
{
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_trunc_tl_i32(cpu_seg_sel[seg_reg], cpu_T[0]);
- tcg_gen_shli_tl(cpu_seg_base[seg_reg], cpu_T[0], 4);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
+ tcg_gen_trunc_tl_i32(cpu_seg_sel[seg_reg], cpu_T0);
+ tcg_gen_shli_tl(cpu_seg_base[seg_reg], cpu_T0, 4);
}
/* move T0 to seg_reg and compute if the CPU state may change. Never
@@ -2179,7 +2179,7 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
/* XXX: optimize by finding processor state dynamically */
gen_update_cc_op(s);
gen_jmp_im(cur_eip);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32);
/* abort translation because the addseg value may change or
because ss32 may change. For R_SS, translation must always
@@ -2256,7 +2256,7 @@ static TCGMemOp gen_pop_T0(DisasContext *s)
addr = cpu_A0;
}
- gen_op_ld_v(s, d_ot, cpu_T[0], addr);
+ gen_op_ld_v(s, d_ot, cpu_T0, addr);
return d_ot;
}
@@ -2300,8 +2300,8 @@ static void gen_popa(DisasContext *s)
}
tcg_gen_addi_tl(cpu_A0, cpu_regs[R_ESP], i * size);
gen_lea_v_seg(s, s_ot, cpu_A0, R_SS, -1);
- gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_v(d_ot, 7 - i, cpu_T[0]);
+ gen_op_ld_v(s, d_ot, cpu_T0, cpu_A0);
+ gen_op_mov_reg_v(d_ot, 7 - i, cpu_T0);
}
gen_stack_update(s, 8 * size);
@@ -2314,8 +2314,8 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
int size = 1 << d_ot;
/* Push BP; compute FrameTemp into T1. */
- tcg_gen_subi_tl(cpu_T[1], cpu_regs[R_ESP], size);
- gen_lea_v_seg(s, a_ot, cpu_T[1], R_SS, -1);
+ tcg_gen_subi_tl(cpu_T1, cpu_regs[R_ESP], size);
+ gen_lea_v_seg(s, a_ot, cpu_T1, R_SS, -1);
gen_op_st_v(s, d_ot, cpu_regs[R_EBP], cpu_A0);
level &= 31;
@@ -2328,23 +2328,23 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)
gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
gen_op_ld_v(s, d_ot, cpu_tmp0, cpu_A0);
- tcg_gen_subi_tl(cpu_A0, cpu_T[1], size * i);
+ tcg_gen_subi_tl(cpu_A0, cpu_T1, size * i);
gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
gen_op_st_v(s, d_ot, cpu_tmp0, cpu_A0);
}
/* Push the current FrameTemp as the last level. */
- tcg_gen_subi_tl(cpu_A0, cpu_T[1], size * level);
+ tcg_gen_subi_tl(cpu_A0, cpu_T1, size * level);
gen_lea_v_seg(s, a_ot, cpu_A0, R_SS, -1);
- gen_op_st_v(s, d_ot, cpu_T[1], cpu_A0);
+ gen_op_st_v(s, d_ot, cpu_T1, cpu_A0);
}
/* Copy the FrameTemp value to EBP. */
- gen_op_mov_reg_v(a_ot, R_EBP, cpu_T[1]);
+ gen_op_mov_reg_v(a_ot, R_EBP, cpu_T1);
/* Compute the final value of ESP. */
- tcg_gen_subi_tl(cpu_T[1], cpu_T[1], esp_addend + size * level);
- gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]);
+ tcg_gen_subi_tl(cpu_T1, cpu_T1, esp_addend + size * level);
+ gen_op_mov_reg_v(a_ot, R_ESP, cpu_T1);
}
static void gen_leave(DisasContext *s)
@@ -2353,12 +2353,12 @@ static void gen_leave(DisasContext *s)
TCGMemOp a_ot = mo_stacksize(s);
gen_lea_v_seg(s, a_ot, cpu_regs[R_EBP], R_SS, -1);
- gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, d_ot, cpu_T0, cpu_A0);
- tcg_gen_addi_tl(cpu_T[1], cpu_regs[R_EBP], 1 << d_ot);
+ tcg_gen_addi_tl(cpu_T1, cpu_regs[R_EBP], 1 << d_ot);
- gen_op_mov_reg_v(d_ot, R_EBP, cpu_T[0]);
- gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]);
+ gen_op_mov_reg_v(d_ot, R_EBP, cpu_T0);
+ gen_op_mov_reg_v(a_ot, R_ESP, cpu_T1);
}
static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
@@ -2919,23 +2919,24 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (b1 & 1) {
gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else {
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0)));
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, MO_32, cpu_T0, cpu_A0);
}
break;
case 0x6e: /* movd mm, ea */
#ifdef TARGET_X86_64
if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
+ tcg_gen_st_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State, fpregs[reg].mmx));
} else
#endif
{
gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
}
break;
@@ -2945,14 +2946,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
- gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
+ gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T0);
} else
#endif
{
gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
}
break;
@@ -2986,16 +2987,24 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x210: /* movss xmm, ea */
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- tcg_gen_movi_tl(cpu_T[0], 0);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
+ gen_op_ld_v(s, MO_32, cpu_T0, cpu_A0);
+ tcg_gen_st32_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_L(0)));
+ tcg_gen_movi_tl(cpu_T0, 0);
+ tcg_gen_st32_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_L(1)));
+ tcg_gen_st32_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_L(2)));
+ tcg_gen_st32_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_L(3)));
} else {
rm = (modrm & 7) | REX_B(s);
- gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
- offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
+ gen_op_movl(offsetof(CPUX86State, xmm_regs[reg].XMM_L(0)),
+ offsetof(CPUX86State, xmm_regs[rm].XMM_L(0)));
}
break;
case 0x310: /* movsd xmm, ea */
@@ -3003,9 +3012,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0)));
- tcg_gen_movi_tl(cpu_T[0], 0);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
+ tcg_gen_movi_tl(cpu_T0, 0);
+ tcg_gen_st32_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_L(2)));
+ tcg_gen_st32_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State,
+ xmm_regs[reg].XMM_L(3)));
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
@@ -3107,28 +3120,29 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x7e: /* movd ea, mm */
#ifdef TARGET_X86_64
if (s->dflag == MO_64) {
- tcg_gen_ld_i64(cpu_T[0], cpu_env,
- offsetof(CPUX86State,fpregs[reg].mmx));
+ tcg_gen_ld_i64(cpu_T0, cpu_env,
+ offsetof(CPUX86State, fpregs[reg].mmx));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
} else
#endif
{
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
- offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State,
+ fpregs[reg].mmx.MMX_L(0)));
gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
}
break;
case 0x17e: /* movd ea, xmm */
#ifdef TARGET_X86_64
if (s->dflag == MO_64) {
- tcg_gen_ld_i64(cpu_T[0], cpu_env,
- offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+ tcg_gen_ld_i64(cpu_T0, cpu_env,
+ offsetof(CPUX86State, xmm_regs[reg].XMM_Q(0)));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
} else
#endif
{
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
- offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, xmm_regs[reg].XMM_L(0)));
gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
}
break;
@@ -3172,8 +3186,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x211: /* movss ea, xmm */
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, xmm_regs[reg].XMM_L(0)));
+ gen_op_st_v(s, MO_32, cpu_T0, cpu_A0);
} else {
rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
@@ -3222,16 +3237,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
val = cpu_ldub_code(env, s->pc++);
if (is_xmm) {
- tcg_gen_movi_tl(cpu_T[0], val);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
- tcg_gen_movi_tl(cpu_T[0], 0);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
+ tcg_gen_movi_tl(cpu_T0, val);
+ tcg_gen_st32_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, xmm_t0.XMM_L(0)));
+ tcg_gen_movi_tl(cpu_T0, 0);
+ tcg_gen_st32_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, xmm_t0.XMM_L(1)));
op1_offset = offsetof(CPUX86State,xmm_t0);
} else {
- tcg_gen_movi_tl(cpu_T[0], val);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
- tcg_gen_movi_tl(cpu_T[0], 0);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
+ tcg_gen_movi_tl(cpu_T0, val);
+ tcg_gen_st32_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, mmx_t0.MMX_L(0)));
+ tcg_gen_movi_tl(cpu_T0, 0);
+ tcg_gen_st32_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, mmx_t0.MMX_L(1)));
op1_offset = offsetof(CPUX86State,mmx_t0);
}
sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
@@ -3296,12 +3315,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
if (ot == MO_32) {
SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32);
} else {
#ifdef TARGET_X86_64
SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1];
- sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]);
+ sse_fn_epl(cpu_env, cpu_ptr0, cpu_T0);
#else
goto illegal_op;
#endif
@@ -3348,8 +3367,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if ((b >> 8) & 1) {
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
} else {
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
+ gen_op_ld_v(s, MO_32, cpu_T0, cpu_A0);
+ tcg_gen_st32_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, xmm_t0.XMM_L(0)));
}
op2_offset = offsetof(CPUX86State,xmm_t0);
} else {
@@ -3361,17 +3381,17 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
SSEFunc_i_ep sse_fn_i_ep =
sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
+ tcg_gen_extu_i32_tl(cpu_T0, cpu_tmp2_i32);
} else {
#ifdef TARGET_X86_64
SSEFunc_l_ep sse_fn_l_ep =
sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
- sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0);
+ sse_fn_l_ep(cpu_T0, cpu_env, cpu_ptr0);
#else
goto illegal_op;
#endif
}
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
case 0xc4: /* pinsrw */
case 0x1c4:
@@ -3380,11 +3400,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
- tcg_gen_st16_tl(cpu_T[0], cpu_env,
+ tcg_gen_st16_tl(cpu_T0,
+ cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
} else {
val &= 3;
- tcg_gen_st16_tl(cpu_T[0], cpu_env,
+ tcg_gen_st16_tl(cpu_T0,
+ cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
}
break;
@@ -3397,16 +3419,18 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (b1) {
val &= 7;
rm = (modrm & 7) | REX_B(s);
- tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
+ tcg_gen_ld16u_tl(cpu_T0,
+ cpu_env,
offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
} else {
val &= 3;
rm = (modrm & 7);
- tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
+ tcg_gen_ld16u_tl(cpu_T0,
+ cpu_env,
offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
}
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
@@ -3553,11 +3577,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_regs[reg]);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
- cpu_T[0], tcg_const_i32(8 << ot));
+ gen_helper_crc32(cpu_T0, cpu_tmp2_i32,
+ cpu_T0, tcg_const_i32(8 << ot));
ot = mo_64_32(s->dflag);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
case 0x1f0: /* crc32 or movbe */
@@ -3582,9 +3606,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm);
if ((b & 1) == 0) {
- tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
+ tcg_gen_qemu_ld_tl(cpu_T0, cpu_A0,
s->mem_index, ot | MO_BE);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
} else {
tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0,
s->mem_index, ot | MO_BE);
@@ -3599,8 +3623,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ tcg_gen_andc_tl(cpu_T0, cpu_regs[s->vex_v], cpu_T0);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -3619,12 +3643,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* Extract START, and shift the operand.
Shifts larger than operand size get zeros. */
tcg_gen_ext8u_tl(cpu_A0, cpu_regs[s->vex_v]);
- tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_A0);
+ tcg_gen_shr_tl(cpu_T0, cpu_T0, cpu_A0);
bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
zero = tcg_const_tl(0);
- tcg_gen_movcond_tl(TCG_COND_LEU, cpu_T[0], cpu_A0, bound,
- cpu_T[0], zero);
+ tcg_gen_movcond_tl(TCG_COND_LEU, cpu_T0, cpu_A0, bound,
+ cpu_T0, zero);
tcg_temp_free(zero);
/* Extract the LEN into a mask. Lengths larger than
@@ -3634,12 +3658,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
tcg_gen_movcond_tl(TCG_COND_LEU, cpu_A0, cpu_A0, bound,
cpu_A0, bound);
tcg_temp_free(bound);
- tcg_gen_movi_tl(cpu_T[1], 1);
- tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_A0);
- tcg_gen_subi_tl(cpu_T[1], cpu_T[1], 1);
- tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_movi_tl(cpu_T1, 1);
+ tcg_gen_shl_tl(cpu_T1, cpu_T1, cpu_A0);
+ tcg_gen_subi_tl(cpu_T1, cpu_T1, 1);
+ tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_T1);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
}
@@ -3653,21 +3677,21 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ tcg_gen_ext8u_tl(cpu_T1, cpu_regs[s->vex_v]);
{
TCGv bound = tcg_const_tl(ot == MO_64 ? 63 : 31);
/* Note that since we're using BMILG (in order to get O
cleared) we need to store the inverse into C. */
tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src,
- cpu_T[1], bound);
- tcg_gen_movcond_tl(TCG_COND_GT, cpu_T[1], cpu_T[1],
- bound, bound, cpu_T[1]);
+ cpu_T1, bound);
+ tcg_gen_movcond_tl(TCG_COND_GT, cpu_T1, cpu_T1,
+ bound, bound, cpu_T1);
tcg_temp_free(bound);
}
tcg_gen_movi_tl(cpu_A0, -1);
- tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T[1]);
- tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_A0);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T1);
+ tcg_gen_andc_tl(cpu_T0, cpu_T0, cpu_A0);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
gen_op_update1_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
@@ -3682,7 +3706,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (ot) {
default:
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EDX]);
tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
cpu_tmp2_i32, cpu_tmp3_i32);
@@ -3692,7 +3716,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],
- cpu_T[0], cpu_regs[R_EDX]);
+ cpu_T0, cpu_regs[R_EDX]);
break;
#endif
}
@@ -3709,11 +3733,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
if (ot == MO_64) {
- tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ tcg_gen_mov_tl(cpu_T1, cpu_regs[s->vex_v]);
} else {
- tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ tcg_gen_ext32u_tl(cpu_T1, cpu_regs[s->vex_v]);
}
- gen_helper_pdep(cpu_regs[reg], cpu_T[0], cpu_T[1]);
+ gen_helper_pdep(cpu_regs[reg], cpu_T0, cpu_T1);
break;
case 0x2f5: /* pext Gy, By, Ey */
@@ -3727,11 +3751,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
if (ot == MO_64) {
- tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ tcg_gen_mov_tl(cpu_T1, cpu_regs[s->vex_v]);
} else {
- tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ tcg_gen_ext32u_tl(cpu_T1, cpu_regs[s->vex_v]);
}
- gen_helper_pext(cpu_regs[reg], cpu_T[0], cpu_T[1]);
+ gen_helper_pext(cpu_regs[reg], cpu_T0, cpu_T1);
break;
case 0x1f6: /* adcx Gy, Ey */
@@ -3790,22 +3814,22 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* If we know TL is 64-bit, and we want a 32-bit
result, just do everything in 64-bit arithmetic. */
tcg_gen_ext32u_i64(cpu_regs[reg], cpu_regs[reg]);
- tcg_gen_ext32u_i64(cpu_T[0], cpu_T[0]);
- tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_regs[reg]);
- tcg_gen_add_i64(cpu_T[0], cpu_T[0], carry_in);
- tcg_gen_ext32u_i64(cpu_regs[reg], cpu_T[0]);
- tcg_gen_shri_i64(carry_out, cpu_T[0], 32);
+ tcg_gen_ext32u_i64(cpu_T0, cpu_T0);
+ tcg_gen_add_i64(cpu_T0, cpu_T0, cpu_regs[reg]);
+ tcg_gen_add_i64(cpu_T0, cpu_T0, carry_in);
+ tcg_gen_ext32u_i64(cpu_regs[reg], cpu_T0);
+ tcg_gen_shri_i64(carry_out, cpu_T0, 32);
break;
#endif
default:
/* Otherwise compute the carry-out in two steps. */
zero = tcg_const_tl(0);
- tcg_gen_add2_tl(cpu_T[0], carry_out,
- cpu_T[0], zero,
+ tcg_gen_add2_tl(cpu_T0, carry_out,
+ cpu_T0, zero,
carry_in, zero);
tcg_gen_add2_tl(cpu_regs[reg], carry_out,
cpu_regs[reg], carry_out,
- cpu_T[0], zero);
+ cpu_T0, zero);
tcg_temp_free(zero);
break;
}
@@ -3824,24 +3848,24 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (ot == MO_64) {
- tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
+ tcg_gen_andi_tl(cpu_T1, cpu_regs[s->vex_v], 63);
} else {
- tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 31);
+ tcg_gen_andi_tl(cpu_T1, cpu_regs[s->vex_v], 31);
}
if (b == 0x1f7) {
- tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_shl_tl(cpu_T0, cpu_T0, cpu_T1);
} else if (b == 0x2f7) {
if (ot != MO_64) {
- tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T0, cpu_T0);
}
- tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_sar_tl(cpu_T0, cpu_T0, cpu_T1);
} else {
if (ot != MO_64) {
- tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext32u_tl(cpu_T0, cpu_T0);
}
- tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_shr_tl(cpu_T0, cpu_T0, cpu_T1);
}
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
case 0x0f3:
@@ -3858,26 +3882,26 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
switch (reg & 7) {
case 1: /* blsr By,Ey */
- tcg_gen_neg_tl(cpu_T[1], cpu_T[0]);
- tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_v(ot, s->vex_v, cpu_T[0]);
+ tcg_gen_neg_tl(cpu_T1, cpu_T0);
+ tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_T1);
+ gen_op_mov_reg_v(ot, s->vex_v, cpu_T0);
gen_op_update2_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
case 2: /* blsmsk By,Ey */
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
- tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1);
- tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
+ tcg_gen_subi_tl(cpu_T0, cpu_T0, 1);
+ tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_cc_src);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
case 3: /* blsi By, Ey */
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
- tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1);
- tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
+ tcg_gen_subi_tl(cpu_T0, cpu_T0, 1);
+ tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_cc_src);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
@@ -3918,22 +3942,22 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
val = cpu_ldub_code(env, s->pc++);
switch (b) {
case 0x14: /* pextrb */
- tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
+ tcg_gen_ld8u_tl(cpu_T0, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
if (mod == 3) {
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
} else {
- tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ tcg_gen_qemu_st_tl(cpu_T0, cpu_A0,
s->mem_index, MO_UB);
}
break;
case 0x15: /* pextrw */
- tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
+ tcg_gen_ld16u_tl(cpu_T0, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_W(val & 7)));
if (mod == 3) {
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
} else {
- tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ tcg_gen_qemu_st_tl(cpu_T0, cpu_A0,
s->mem_index, MO_LEUW);
}
break;
@@ -3965,23 +3989,23 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
break;
case 0x17: /* extractps */
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
if (mod == 3) {
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
} else {
- tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
+ tcg_gen_qemu_st_tl(cpu_T0, cpu_A0,
s->mem_index, MO_LEUL);
}
break;
case 0x20: /* pinsrb */
if (mod == 3) {
- gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
+ gen_op_mov_v_reg(MO_32, cpu_T0, rm);
} else {
- tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
+ tcg_gen_qemu_ld_tl(cpu_T0, cpu_A0,
s->mem_index, MO_UB);
}
- tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
+ tcg_gen_st8_tl(cpu_T0, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
break;
case 0x21: /* insertps */
@@ -4095,13 +4119,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
b = cpu_ldub_code(env, s->pc++);
if (ot == MO_64) {
- tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], b & 63);
+ tcg_gen_rotri_tl(cpu_T0, cpu_T0, b & 63);
} else {
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, b & 31);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
+ tcg_gen_extu_i32_tl(cpu_T0, cpu_tmp2_i32);
}
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
default:
@@ -4133,8 +4157,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* specific case for SSE single instructions */
if (b1 == 2) {
/* 32 bit access */
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
+ gen_op_ld_v(s, MO_32, cpu_T0, cpu_A0);
+ tcg_gen_st32_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, xmm_t0.XMM_L(0)));
} else {
/* 64 bit access */
gen_ldq_env_A0(s, offsetof(CPUX86State,
@@ -4425,13 +4450,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
xor_zero:
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
- tcg_gen_movi_tl(cpu_T[0], 0);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ tcg_gen_movi_tl(cpu_T0, 0);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
} else {
opreg = rm;
}
- gen_op_mov_v_reg(ot, cpu_T[1], reg);
+ gen_op_mov_v_reg(ot, cpu_T1, reg);
gen_op(s, op, ot, opreg);
break;
case 1: /* OP Gv, Ev */
@@ -4441,17 +4466,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
- gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
- gen_op_mov_v_reg(ot, cpu_T[1], rm);
+ gen_op_mov_v_reg(ot, cpu_T1, rm);
}
gen_op(s, op, ot, reg);
break;
case 2: /* OP A, Iv */
val = insn_get(env, s, ot);
- tcg_gen_movi_tl(cpu_T[1], val);
+ tcg_gen_movi_tl(cpu_T1, val);
gen_op(s, op, ot, OR_EAX);
break;
}
@@ -4496,7 +4521,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = (int8_t)insn_get(env, s, MO_8);
break;
}
- tcg_gen_movi_tl(cpu_T[1], val);
+ tcg_gen_movi_tl(cpu_T1, val);
gen_op(s, op, ot, opreg);
}
break;
@@ -4523,32 +4548,32 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (op == 0)
s->rip_offset = insn_const_size(ot);
gen_lea_modrm(env, s, modrm);
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], rm);
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
}
switch(op) {
case 0: /* test */
val = insn_get(env, s, ot);
- tcg_gen_movi_tl(cpu_T[1], val);
+ tcg_gen_movi_tl(cpu_T1, val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 2: /* not */
- tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_not_tl(cpu_T0, cpu_T0);
if (mod != 3) {
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
}
break;
case 3: /* neg */
- tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_neg_tl(cpu_T0, cpu_T0);
if (mod != 3) {
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
}
gen_op_update_neg_cc();
set_cc_op(s, CC_OP_SUBB + ot);
@@ -4556,32 +4581,32 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 4: /* mul */
switch(ot) {
case MO_8:
- gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
- tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
+ gen_op_mov_v_reg(MO_8, cpu_T1, R_EAX);
+ tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
+ tcg_gen_ext8u_tl(cpu_T1, cpu_T1);
/* XXX: use 32 bit mul which could be faster */
- tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
+ tcg_gen_mul_tl(cpu_T0, cpu_T0, cpu_T1);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T0);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
+ tcg_gen_andi_tl(cpu_cc_src, cpu_T0, 0xff00);
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
+ gen_op_mov_v_reg(MO_16, cpu_T1, R_EAX);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
+ tcg_gen_ext16u_tl(cpu_T1, cpu_T1);
/* XXX: use 32 bit mul which could be faster */
- tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_mul_tl(cpu_T0, cpu_T0, cpu_T1);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T0);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
+ tcg_gen_shri_tl(cpu_T0, cpu_T0, 16);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T0);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
set_cc_op(s, CC_OP_MULW);
break;
default:
case MO_32:
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
cpu_tmp2_i32, cpu_tmp3_i32);
@@ -4594,7 +4619,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
- cpu_T[0], cpu_regs[R_EAX]);
+ cpu_T0, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULQ);
@@ -4605,34 +4630,34 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 5: /* imul */
switch(ot) {
case MO_8:
- gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
- tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
+ gen_op_mov_v_reg(MO_8, cpu_T1, R_EAX);
+ tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
+ tcg_gen_ext8s_tl(cpu_T1, cpu_T1);
/* XXX: use 32 bit mul which could be faster */
- tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
- tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
+ tcg_gen_mul_tl(cpu_T0, cpu_T0, cpu_T1);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T0);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
+ tcg_gen_ext8s_tl(cpu_tmp0, cpu_T0);
+ tcg_gen_sub_tl(cpu_cc_src, cpu_T0, cpu_tmp0);
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
- tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
+ gen_op_mov_v_reg(MO_16, cpu_T1, R_EAX);
+ tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
+ tcg_gen_ext16s_tl(cpu_T1, cpu_T1);
/* XXX: use 32 bit mul which could be faster */
- tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
- tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
- tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
+ tcg_gen_mul_tl(cpu_T0, cpu_T0, cpu_T1);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T0);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
+ tcg_gen_ext16s_tl(cpu_tmp0, cpu_T0);
+ tcg_gen_sub_tl(cpu_cc_src, cpu_T0, cpu_tmp0);
+ tcg_gen_shri_tl(cpu_T0, cpu_T0, 16);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T0);
set_cc_op(s, CC_OP_MULW);
break;
default:
case MO_32:
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
cpu_tmp2_i32, cpu_tmp3_i32);
@@ -4647,7 +4672,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
#ifdef TARGET_X86_64
case MO_64:
tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
- cpu_T[0], cpu_regs[R_EAX]);
+ cpu_T0, cpu_regs[R_EAX]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
tcg_gen_sari_tl(cpu_cc_src, cpu_regs[R_EAX], 63);
tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_regs[R_EDX]);
@@ -4660,21 +4685,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(ot) {
case MO_8:
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_divb_AL(cpu_env, cpu_T[0]);
+ gen_helper_divb_AL(cpu_env, cpu_T0);
break;
case MO_16:
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_divw_AX(cpu_env, cpu_T[0]);
+ gen_helper_divw_AX(cpu_env, cpu_T0);
break;
default:
case MO_32:
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_divl_EAX(cpu_env, cpu_T[0]);
+ gen_helper_divl_EAX(cpu_env, cpu_T0);
break;
#ifdef TARGET_X86_64
case MO_64:
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_divq_EAX(cpu_env, cpu_T[0]);
+ gen_helper_divq_EAX(cpu_env, cpu_T0);
break;
#endif
}
@@ -4683,21 +4708,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(ot) {
case MO_8:
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_idivb_AL(cpu_env, cpu_T[0]);
+ gen_helper_idivb_AL(cpu_env, cpu_T0);
break;
case MO_16:
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_idivw_AX(cpu_env, cpu_T[0]);
+ gen_helper_idivw_AX(cpu_env, cpu_T0);
break;
default:
case MO_32:
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_idivl_EAX(cpu_env, cpu_T[0]);
+ gen_helper_idivl_EAX(cpu_env, cpu_T0);
break;
#ifdef TARGET_X86_64
case MO_64:
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_idivq_EAX(cpu_env, cpu_T[0]);
+ gen_helper_idivq_EAX(cpu_env, cpu_T0);
break;
#endif
}
@@ -4732,9 +4757,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
if (op >= 2 && op != 3 && op != 5)
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], rm);
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
}
switch(op) {
@@ -4755,29 +4780,29 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
if (dflag == MO_16) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
}
next_eip = s->pc - s->cs_base;
- tcg_gen_movi_tl(cpu_T[1], next_eip);
- gen_push_v(s, cpu_T[1]);
- gen_op_jmp_v(cpu_T[0]);
+ tcg_gen_movi_tl(cpu_T1, next_eip);
+ gen_push_v(s, cpu_T1);
+ gen_op_jmp_v(cpu_T0);
gen_eob(s);
break;
case 3: /* lcall Ev */
- gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
gen_add_A0_im(s, 1 << ot);
- gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, MO_16, cpu_T0, cpu_A0);
do_lcall:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
+ gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T1,
tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - pc_start));
} else {
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
+ gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T1,
tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
}
@@ -4785,30 +4810,30 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 4: /* jmp Ev */
if (dflag == MO_16) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
}
- gen_op_jmp_v(cpu_T[0]);
+ gen_op_jmp_v(cpu_T0);
gen_eob(s);
break;
case 5: /* ljmp Ev */
- gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
gen_add_A0_im(s, 1 << ot);
- gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, MO_16, cpu_T0, cpu_A0);
do_ljmp:
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
+ gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T1,
tcg_const_i32(s->pc - pc_start));
} else {
gen_op_movl_seg_T0_vm(R_CS);
- gen_op_jmp_v(cpu_T[1]);
+ gen_op_jmp_v(cpu_T1);
}
gen_eob(s);
break;
case 6: /* push Ev */
- gen_push_v(s, cpu_T[0]);
+ gen_push_v(s, cpu_T0);
break;
default:
goto illegal_op;
@@ -4823,7 +4848,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_v_reg(ot, cpu_T[1], reg);
+ gen_op_mov_v_reg(ot, cpu_T1, reg);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -4833,8 +4858,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
- gen_op_mov_v_reg(ot, cpu_T[0], OR_EAX);
- tcg_gen_movi_tl(cpu_T[1], val);
+ gen_op_mov_v_reg(ot, cpu_T0, OR_EAX);
+ tcg_gen_movi_tl(cpu_T1, val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -4843,20 +4868,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
- gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
- tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
+ gen_op_mov_v_reg(MO_32, cpu_T0, R_EAX);
+ tcg_gen_ext32s_tl(cpu_T0, cpu_T0);
+ gen_op_mov_reg_v(MO_64, R_EAX, cpu_T0);
break;
#endif
case MO_32:
- gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
- tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
+ gen_op_mov_v_reg(MO_16, cpu_T0, R_EAX);
+ tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
+ gen_op_mov_reg_v(MO_32, R_EAX, cpu_T0);
break;
case MO_16:
- gen_op_mov_v_reg(MO_8, cpu_T[0], R_EAX);
- tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
+ gen_op_mov_v_reg(MO_8, cpu_T0, R_EAX);
+ tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T0);
break;
default:
tcg_abort();
@@ -4866,22 +4891,22 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch (dflag) {
#ifdef TARGET_X86_64
case MO_64:
- gen_op_mov_v_reg(MO_64, cpu_T[0], R_EAX);
- tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
- gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
+ gen_op_mov_v_reg(MO_64, cpu_T0, R_EAX);
+ tcg_gen_sari_tl(cpu_T0, cpu_T0, 63);
+ gen_op_mov_reg_v(MO_64, R_EDX, cpu_T0);
break;
#endif
case MO_32:
- gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
- tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
- gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
+ gen_op_mov_v_reg(MO_32, cpu_T0, R_EAX);
+ tcg_gen_ext32s_tl(cpu_T0, cpu_T0);
+ tcg_gen_sari_tl(cpu_T0, cpu_T0, 31);
+ gen_op_mov_reg_v(MO_32, R_EDX, cpu_T0);
break;
case MO_16:
- gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
- tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
- gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
+ gen_op_mov_v_reg(MO_16, cpu_T0, R_EAX);
+ tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
+ tcg_gen_sari_tl(cpu_T0, cpu_T0, 15);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T0);
break;
default:
tcg_abort();
@@ -4900,25 +4925,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (b == 0x69) {
val = insn_get(env, s, ot);
- tcg_gen_movi_tl(cpu_T[1], val);
+ tcg_gen_movi_tl(cpu_T1, val);
} else if (b == 0x6b) {
val = (int8_t)insn_get(env, s, MO_8);
- tcg_gen_movi_tl(cpu_T[1], val);
+ tcg_gen_movi_tl(cpu_T1, val);
} else {
- gen_op_mov_v_reg(ot, cpu_T[1], reg);
+ gen_op_mov_v_reg(ot, cpu_T1, reg);
}
switch (ot) {
#ifdef TARGET_X86_64
case MO_64:
- tcg_gen_muls2_i64(cpu_regs[reg], cpu_T[1], cpu_T[0], cpu_T[1]);
+ tcg_gen_muls2_i64(cpu_regs[reg], cpu_T1, cpu_T0, cpu_T1);
tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);
- tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_T[1]);
+ tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_T1);
break;
#endif
case MO_32:
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
cpu_tmp2_i32, cpu_tmp3_i32);
tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
@@ -4928,14 +4953,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32);
break;
default:
- tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
+ tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
+ tcg_gen_ext16s_tl(cpu_T1, cpu_T1);
/* XXX: use 32 bit mul which could be faster */
- tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
- tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ tcg_gen_mul_tl(cpu_T0, cpu_T0, cpu_T1);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
+ tcg_gen_ext16s_tl(cpu_tmp0, cpu_T0);
+ tcg_gen_sub_tl(cpu_cc_src, cpu_T0, cpu_tmp0);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
}
set_cc_op(s, CC_OP_MULB + ot);
@@ -4948,18 +4973,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_v_reg(ot, cpu_T[0], reg);
- gen_op_mov_v_reg(ot, cpu_T[1], rm);
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_v(ot, reg, cpu_T[1]);
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_v_reg(ot, cpu_T0, reg);
+ gen_op_mov_v_reg(ot, cpu_T1, rm);
+ tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1);
+ gen_op_mov_reg_v(ot, reg, cpu_T1);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_v_reg(ot, cpu_T[0], reg);
- gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_v(ot, reg, cpu_T[1]);
+ gen_op_mov_v_reg(ot, cpu_T0, reg);
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
+ tcg_gen_add_tl(cpu_T0, cpu_T0, cpu_T1);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
+ gen_op_mov_reg_v(ot, reg, cpu_T1);
}
gen_op_update2_cc();
set_cc_op(s, CC_OP_ADDB + ot);
@@ -5049,14 +5074,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
- gen_op_mov_v_reg(MO_32, cpu_T[0], (b & 7) | REX_B(s));
- gen_push_v(s, cpu_T[0]);
+ gen_op_mov_v_reg(MO_32, cpu_T0, (b & 7) | REX_B(s));
+ gen_push_v(s, cpu_T0);
break;
case 0x58 ... 0x5f: /* pop */
ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
- gen_op_mov_reg_v(ot, (b & 7) | REX_B(s), cpu_T[0]);
+ gen_op_mov_reg_v(ot, (b & 7) | REX_B(s), cpu_T0);
break;
case 0x60: /* pusha */
if (CODE64(s))
@@ -5075,8 +5100,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = insn_get(env, s, ot);
else
val = (int8_t)insn_get(env, s, MO_8);
- tcg_gen_movi_tl(cpu_T[0], val);
- gen_push_v(s, cpu_T[0]);
+ tcg_gen_movi_tl(cpu_T0, val);
+ gen_push_v(s, cpu_T0);
break;
case 0x8f: /* pop Ev */
modrm = cpu_ldub_code(env, s->pc++);
@@ -5086,7 +5111,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
} else {
/* NOTE: order is important too for MMU exceptions */
s->popl_esp_hack = 1 << ot;
@@ -5114,12 +5139,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (CODE64(s))
goto illegal_op;
gen_op_movl_T0_seg(b >> 3);
- gen_push_v(s, cpu_T[0]);
+ gen_push_v(s, cpu_T0);
break;
case 0x1a0: /* push fs */
case 0x1a8: /* push gs */
gen_op_movl_T0_seg((b >> 3) & 7);
- gen_push_v(s, cpu_T[0]);
+ gen_push_v(s, cpu_T0);
break;
case 0x07: /* pop es */
case 0x17: /* pop ss */
@@ -5175,11 +5200,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_lea_modrm(env, s, modrm);
}
val = insn_get(env, s, ot);
- tcg_gen_movi_tl(cpu_T[0], val);
+ tcg_gen_movi_tl(cpu_T0, val);
if (mod != 3) {
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_reg_v(ot, (modrm & 7) | REX_B(s), cpu_T[0]);
+ gen_op_mov_reg_v(ot, (modrm & 7) | REX_B(s), cpu_T0);
}
break;
case 0x8a:
@@ -5189,7 +5214,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
case 0x8e: /* mov seg, Gv */
modrm = cpu_ldub_code(env, s->pc++);
@@ -5243,27 +5268,27 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_v_reg(ot, cpu_T[0], rm);
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
switch (s_ot) {
case MO_UB:
- tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
break;
case MO_SB:
- tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
break;
case MO_UW:
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
break;
default:
case MO_SW:
- tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
+ tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
break;
}
- gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T0);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
+ gen_op_ld_v(s, s_ot, cpu_T0, cpu_A0);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T0);
}
}
break;
@@ -5306,27 +5331,27 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_movi_tl(cpu_A0, offset_addr);
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], R_EAX);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_mov_v_reg(ot, cpu_T0, R_EAX);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
}
}
break;
case 0xd7: /* xlat */
tcg_gen_mov_tl(cpu_A0, cpu_regs[R_EBX]);
- tcg_gen_ext8u_tl(cpu_T[0], cpu_regs[R_EAX]);
- tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
+ tcg_gen_ext8u_tl(cpu_T0, cpu_regs[R_EAX]);
+ tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T0);
gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
- gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
- gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
+ gen_op_ld_v(s, MO_8, cpu_T0, cpu_A0);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T0);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
- tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_v(MO_8, (b & 7) | REX_B(s), cpu_T[0]);
+ tcg_gen_movi_tl(cpu_T0, val);
+ gen_op_mov_reg_v(MO_8, (b & 7) | REX_B(s), cpu_T0);
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
@@ -5336,16 +5361,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tmp = cpu_ldq_code(env, s->pc);
s->pc += 8;
reg = (b & 7) | REX_B(s);
- tcg_gen_movi_tl(cpu_T[0], tmp);
- gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
+ tcg_gen_movi_tl(cpu_T0, tmp);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T0);
} else
#endif
{
ot = dflag;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
- tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ tcg_gen_movi_tl(cpu_T0, val);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
}
break;
@@ -5364,21 +5389,21 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
do_xchg_reg:
- gen_op_mov_v_reg(ot, cpu_T[0], reg);
- gen_op_mov_v_reg(ot, cpu_T[1], rm);
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
- gen_op_mov_reg_v(ot, reg, cpu_T[1]);
+ gen_op_mov_v_reg(ot, cpu_T0, reg);
+ gen_op_mov_v_reg(ot, cpu_T1, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
+ gen_op_mov_reg_v(ot, reg, cpu_T1);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T0, reg);
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
- gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
- gen_op_mov_reg_v(ot, reg, cpu_T[1]);
+ gen_op_mov_reg_v(ot, reg, cpu_T1);
}
break;
case 0xc4: /* les Gv */
@@ -5405,13 +5430,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod == 3)
goto illegal_op;
gen_lea_modrm(env, s, modrm);
- gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T1, cpu_A0);
gen_add_A0_im(s, 1 << ot);
/* load the segment first to handle exceptions properly */
- gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, MO_16, cpu_T0, cpu_A0);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
- gen_op_mov_reg_v(ot, reg, cpu_T[1]);
+ gen_op_mov_reg_v(ot, reg, cpu_T1);
if (s->is_jmp) {
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -5490,7 +5515,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
opreg = rm;
}
- gen_op_mov_v_reg(ot, cpu_T[1], reg);
+ gen_op_mov_v_reg(ot, cpu_T1, reg);
if (shift) {
TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++));
@@ -5968,8 +5993,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
switch(rm) {
case 0:
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
- tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
+ tcg_gen_extu_i32_tl(cpu_T0, cpu_tmp2_i32);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T0);
break;
default:
goto illegal_op;
@@ -6078,7 +6103,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x6c: /* insS */
case 0x6d:
ot = mo_b_d32(b, dflag);
- tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
@@ -6093,7 +6118,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x6e: /* outsS */
case 0x6f:
ot = mo_b_d32(b, dflag);
- tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
@@ -6118,8 +6143,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (use_icount)
gen_io_start();
tcg_gen_movi_i32(cpu_tmp2_i32, val);
- gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
- gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
+ gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T1);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@@ -6131,12 +6156,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
val = cpu_ldub_code(env, s->pc++);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T1, R_EAX);
if (use_icount)
gen_io_start();
tcg_gen_movi_i32(cpu_tmp2_i32, val);
- tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
if (use_icount) {
gen_io_end();
@@ -6146,14 +6171,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xec:
case 0xed:
ot = mo_b_d32(b, dflag);
- tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (use_icount)
gen_io_start();
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
- gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
+ gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T1);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@@ -6162,15 +6187,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0xee:
case 0xef:
ot = mo_b_d32(b, dflag);
- tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
+ tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T1, R_EAX);
if (use_icount)
gen_io_start();
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
- tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
if (use_icount) {
gen_io_end();
@@ -6186,14 +6211,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = gen_pop_T0(s);
gen_stack_update(s, val + (1 << ot));
/* Note that gen_pop_T0 uses a zero-extending load. */
- gen_op_jmp_v(cpu_T[0]);
+ gen_op_jmp_v(cpu_T0);
gen_eob(s);
break;
case 0xc3: /* ret */
ot = gen_pop_T0(s);
gen_pop_update(s, ot);
/* Note that gen_pop_T0 uses a zero-extending load. */
- gen_op_jmp_v(cpu_T[0]);
+ gen_op_jmp_v(cpu_T0);
gen_eob(s);
break;
case 0xca: /* lret im */
@@ -6208,13 +6233,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, dflag, cpu_T0, cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
- gen_op_jmp_v(cpu_T[0]);
+ gen_op_jmp_v(cpu_T0);
/* pop selector */
gen_add_A0_im(s, 1 << dflag);
- gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, dflag, cpu_T0, cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
gen_stack_update(s, val + (2 << dflag));
@@ -6260,8 +6285,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else if (!CODE64(s)) {
tval &= 0xffffffff;
}
- tcg_gen_movi_tl(cpu_T[0], next_eip);
- gen_push_v(s, cpu_T[0]);
+ tcg_gen_movi_tl(cpu_T0, next_eip);
+ gen_push_v(s, cpu_T0);
gen_jmp(s, tval);
}
break;
@@ -6275,8 +6300,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
- tcg_gen_movi_tl(cpu_T[0], selector);
- tcg_gen_movi_tl(cpu_T[1], offset);
+ tcg_gen_movi_tl(cpu_T0, selector);
+ tcg_gen_movi_tl(cpu_T1, offset);
}
goto do_lcall;
case 0xe9: /* jmp im */
@@ -6303,8 +6328,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
- tcg_gen_movi_tl(cpu_T[0], selector);
- tcg_gen_movi_tl(cpu_T[1], offset);
+ tcg_gen_movi_tl(cpu_T0, selector);
+ tcg_gen_movi_tl(cpu_T1, offset);
}
goto do_ljmp;
case 0xeb: /* jmp Jb */
@@ -6335,7 +6360,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x190 ... 0x19f: /* setcc Gv */
modrm = cpu_ldub_code(env, s->pc++);
- gen_setcc1(s, b, cpu_T[0]);
+ gen_setcc1(s, b, cpu_T0);
gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1);
break;
case 0x140 ... 0x14f: /* cmov Gv, Ev */
@@ -6356,8 +6381,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
gen_update_cc_op(s);
- gen_helper_read_eflags(cpu_T[0], cpu_env);
- gen_push_v(s, cpu_T[0]);
+ gen_helper_read_eflags(cpu_T0, cpu_env);
+ gen_push_v(s, cpu_T0);
}
break;
case 0x9d: /* popf */
@@ -6368,13 +6393,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = gen_pop_T0(s);
if (s->cpl == 0) {
if (dflag != MO_16) {
- gen_helper_write_eflags(cpu_env, cpu_T[0],
+ gen_helper_write_eflags(cpu_env, cpu_T0,
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK |
IF_MASK |
IOPL_MASK)));
} else {
- gen_helper_write_eflags(cpu_env, cpu_T[0],
+ gen_helper_write_eflags(cpu_env, cpu_T0,
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK |
IF_MASK | IOPL_MASK)
@@ -6383,14 +6408,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
if (s->cpl <= s->iopl) {
if (dflag != MO_16) {
- gen_helper_write_eflags(cpu_env, cpu_T[0],
+ gen_helper_write_eflags(cpu_env, cpu_T0,
tcg_const_i32((TF_MASK |
AC_MASK |
ID_MASK |
NT_MASK |
IF_MASK)));
} else {
- gen_helper_write_eflags(cpu_env, cpu_T[0],
+ gen_helper_write_eflags(cpu_env, cpu_T0,
tcg_const_i32((TF_MASK |
AC_MASK |
ID_MASK |
@@ -6400,11 +6425,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
} else {
if (dflag != MO_16) {
- gen_helper_write_eflags(cpu_env, cpu_T[0],
+ gen_helper_write_eflags(cpu_env, cpu_T0,
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK)));
} else {
- gen_helper_write_eflags(cpu_env, cpu_T[0],
+ gen_helper_write_eflags(cpu_env, cpu_T0,
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK)
& 0xffff));
@@ -6421,19 +6446,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
- gen_op_mov_v_reg(MO_8, cpu_T[0], R_AH);
+ gen_op_mov_v_reg(MO_8, cpu_T0, R_AH);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
- tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
+ tcg_gen_andi_tl(cpu_T0, cpu_T0, CC_S | CC_Z | CC_A | CC_P | CC_C);
+ tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T0);
break;
case 0x9f: /* lahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
- tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
- gen_op_mov_reg_v(MO_8, R_AH, cpu_T[0]);
+ tcg_gen_ori_tl(cpu_T0, cpu_cc_src, 0x02);
+ gen_op_mov_reg_v(MO_8, R_AH, cpu_T0);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
@@ -6467,13 +6492,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (mod != 3) {
s->rip_offset = 1;
gen_lea_modrm(env, s, modrm);
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], rm);
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
}
/* load shift */
val = cpu_ldub_code(env, s->pc++);
- tcg_gen_movi_tl(cpu_T[1], val);
+ tcg_gen_movi_tl(cpu_T1, val);
if (op < 4)
goto illegal_op;
op -= 4;
@@ -6495,52 +6520,52 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_v_reg(MO_32, cpu_T[1], reg);
+ gen_op_mov_v_reg(MO_32, cpu_T1, reg);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
/* specific case: we need to add a displacement */
- gen_exts(ot, cpu_T[1]);
- tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
+ gen_exts(ot, cpu_T1);
+ tcg_gen_sari_tl(cpu_tmp0, cpu_T1, 3 + ot);
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
- gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_v_reg(ot, cpu_T[0], rm);
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
}
bt_op:
- tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
+ tcg_gen_andi_tl(cpu_T1, cpu_T1, (1 << (3 + ot)) - 1);
switch(op) {
case 0:
- tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
+ tcg_gen_shr_tl(cpu_cc_src, cpu_T0, cpu_T1);
tcg_gen_movi_tl(cpu_cc_dst, 0);
break;
case 1:
- tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
+ tcg_gen_shr_tl(cpu_tmp4, cpu_T0, cpu_T1);
tcg_gen_movi_tl(cpu_tmp0, 1);
- tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
+ tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
+ tcg_gen_or_tl(cpu_T0, cpu_T0, cpu_tmp0);
break;
case 2:
- tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
+ tcg_gen_shr_tl(cpu_tmp4, cpu_T0, cpu_T1);
tcg_gen_movi_tl(cpu_tmp0, 1);
- tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
+ tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
- tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
+ tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_tmp0);
break;
default:
case 3:
- tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
+ tcg_gen_shr_tl(cpu_tmp4, cpu_T0, cpu_T1);
tcg_gen_movi_tl(cpu_tmp0, 1);
- tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
- tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
+ tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T1);
+ tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_tmp0);
break;
}
set_cc_op(s, CC_OP_SARB + ot);
if (op != 0) {
if (mod != 3) {
- gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, ot, cpu_T0, cpu_A0);
} else {
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
}
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_movi_tl(cpu_cc_dst, 0);
@@ -6552,7 +6577,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_extu(ot, cpu_T[0]);
+ gen_extu(ot, cpu_T0);
/* Note that lzcnt and tzcnt are in different extensions. */
if ((prefixes & PREFIX_REPZ)
@@ -6560,18 +6585,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
? s->cpuid_ext3_features & CPUID_EXT3_ABM
: s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) {
int size = 8 << ot;
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
if (b & 1) {
/* For lzcnt, reduce the target_ulong result by the
number of zeros that we expect to find at the top. */
- gen_helper_clz(cpu_T[0], cpu_T[0]);
- tcg_gen_subi_tl(cpu_T[0], cpu_T[0], TARGET_LONG_BITS - size);
+ gen_helper_clz(cpu_T0, cpu_T0);
+ tcg_gen_subi_tl(cpu_T0, cpu_T0, TARGET_LONG_BITS - size);
} else {
/* For tzcnt, a zero input must return the operand size:
force all bits outside the operand size to 1. */
target_ulong mask = (target_ulong)-2 << (size - 1);
- tcg_gen_ori_tl(cpu_T[0], cpu_T[0], mask);
- gen_helper_ctz(cpu_T[0], cpu_T[0]);
+ tcg_gen_ori_tl(cpu_T0, cpu_T0, mask);
+ gen_helper_ctz(cpu_T0, cpu_T0);
}
/* For lzcnt/tzcnt, C and Z bits are defined and are
related to the result. */
@@ -6580,24 +6605,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
/* For bsr/bsf, only the Z bit is defined and it is related
to the input and not the result. */
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
set_cc_op(s, CC_OP_LOGICB + ot);
if (b & 1) {
/* For bsr, return the bit index of the first 1 bit,
not the count of leading zeros. */
- gen_helper_clz(cpu_T[0], cpu_T[0]);
- tcg_gen_xori_tl(cpu_T[0], cpu_T[0], TARGET_LONG_BITS - 1);
+ gen_helper_clz(cpu_T0, cpu_T0);
+ tcg_gen_xori_tl(cpu_T0, cpu_T0, TARGET_LONG_BITS - 1);
} else {
- gen_helper_ctz(cpu_T[0], cpu_T[0]);
+ gen_helper_ctz(cpu_T0, cpu_T0);
}
/* ??? The manual says that the output is undefined when the
input is zero, but real hardware leaves it unchanged, and
real programs appear to depend on that. */
tcg_gen_movi_tl(cpu_tmp0, 0);
- tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[0], cpu_cc_dst, cpu_tmp0,
- cpu_regs[reg], cpu_T[0]);
+ tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T0, cpu_cc_dst, cpu_tmp0,
+ cpu_regs[reg], cpu_T0);
}
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
break;
/************************/
/* bcd */
@@ -6753,10 +6778,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T0, reg);
gen_lea_modrm(env, s, modrm);
gen_jmp_im(pc_start - s->cs_base);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
if (ot == MO_16) {
gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32);
} else {
@@ -6767,24 +6792,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == MO_64) {
- gen_op_mov_v_reg(MO_64, cpu_T[0], reg);
- tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
+ gen_op_mov_v_reg(MO_64, cpu_T0, reg);
+ tcg_gen_bswap64_i64(cpu_T0, cpu_T0);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T0);
} else
#endif
{
- gen_op_mov_v_reg(MO_32, cpu_T[0], reg);
- tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
+ gen_op_mov_v_reg(MO_32, cpu_T0, reg);
+ tcg_gen_ext32u_tl(cpu_T0, cpu_T0);
+ tcg_gen_bswap32_tl(cpu_T0, cpu_T0);
+ gen_op_mov_reg_v(MO_32, reg, cpu_T0);
}
break;
case 0xd6: /* salc */
if (CODE64(s))
goto illegal_op;
- gen_compute_eflags_c(s, cpu_T[0]);
- tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
+ gen_compute_eflags_c(s, cpu_T0);
+ tcg_gen_neg_tl(cpu_T0, cpu_T0);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T0);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
@@ -6933,7 +6958,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (!s->pe || s->vm86)
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, ldt.selector));
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
@@ -6946,7 +6972,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_jmp_im(pc_start - s->cs_base);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_lldt(cpu_env, cpu_tmp2_i32);
}
break;
@@ -6954,7 +6980,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (!s->pe || s->vm86)
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, tr.selector));
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
@@ -6967,7 +6994,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_jmp_im(pc_start - s->cs_base);
- tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0);
gen_helper_ltr(cpu_env, cpu_tmp2_i32);
}
break;
@@ -6978,9 +7005,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_update_cc_op(s);
if (op == 4) {
- gen_helper_verr(cpu_env, cpu_T[0]);
+ gen_helper_verr(cpu_env, cpu_T0);
} else {
- gen_helper_verw(cpu_env, cpu_T[0]);
+ gen_helper_verw(cpu_env, cpu_T0);
}
set_cc_op(s, CC_OP_EFLAGS);
break;
@@ -6999,14 +7026,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm);
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_ld32u_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State, gdt.limit));
+ gen_op_st_v(s, MO_16, cpu_T0, cpu_A0);
gen_add_A0_im(s, 2);
- tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
+ tcg_gen_ld_tl(cpu_T0, cpu_env, offsetof(CPUX86State, gdt.base));
if (dflag == MO_16) {
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ tcg_gen_andi_tl(cpu_T0, cpu_T0, 0xffffff);
}
- gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, CODE64(s) + MO_32, cpu_T0, cpu_A0);
break;
case 1:
if (mod == 3) {
@@ -7055,14 +7083,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else { /* sidt */
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm);
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
+ tcg_gen_ld32u_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State, idt.limit));
+ gen_op_st_v(s, MO_16, cpu_T0, cpu_A0);
gen_add_A0_im(s, 2);
- tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
+ tcg_gen_ld_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State, idt.base));
if (dflag == MO_16) {
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ tcg_gen_andi_tl(cpu_T0, cpu_T0, 0xffffff);
}
- gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
+ gen_op_st_v(s, CODE64(s) + MO_32, cpu_T0, cpu_A0);
}
break;
case 2: /* lgdt */
@@ -7157,27 +7187,31 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_svm_check_intercept(s, pc_start,
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
gen_lea_modrm(env, s, modrm);
- gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
+ gen_op_ld_v(s, MO_16, cpu_T1, cpu_A0);
gen_add_A0_im(s, 2);
- gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T0, cpu_A0);
if (dflag == MO_16) {
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
+ tcg_gen_andi_tl(cpu_T0, cpu_T0, 0xffffff);
}
if (op == 2) {
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
- tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
+ tcg_gen_st_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, gdt.base));
+ tcg_gen_st32_tl(cpu_T1, cpu_env,
+ offsetof(CPUX86State, gdt.limit));
} else {
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
- tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
+ tcg_gen_st_tl(cpu_T0, cpu_env,
+ offsetof(CPUX86State, idt.base));
+ tcg_gen_st32_tl(cpu_T1, cpu_env,
+ offsetof(CPUX86State, idt.limit));
}
}
break;
case 4: /* smsw */
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]) + 4);
#else
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
+ tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]));
#endif
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1);
break;
@@ -7187,7 +7221,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
- gen_helper_lmsw(cpu_env, cpu_T[0]);
+ gen_helper_lmsw(cpu_env, cpu_T0);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
}
@@ -7212,10 +7246,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
if (s->cpl != 0) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- tcg_gen_mov_tl(cpu_T[0], cpu_seg_base[R_GS]);
+ tcg_gen_mov_tl(cpu_T0, cpu_seg_base[R_GS]);
tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env,
offsetof(CPUX86State, kernelgsbase));
- tcg_gen_st_tl(cpu_T[0], cpu_env,
+ tcg_gen_st_tl(cpu_T0, cpu_env,
offsetof(CPUX86State, kernelgsbase));
}
break;
@@ -7266,15 +7300,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
+ gen_op_mov_v_reg(MO_32, cpu_T0, rm);
/* sign extend */
if (d_ot == MO_64)
- tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
+ tcg_gen_ext32s_tl(cpu_T0, cpu_T0);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T0);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
- gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
+ gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T0, cpu_A0);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T0);
}
} else
#endif
@@ -7339,9 +7373,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
t0 = tcg_temp_local_new();
gen_update_cc_op(s);
if (b == 0x102) {
- gen_helper_lar(t0, cpu_env, cpu_T[0]);
+ gen_helper_lar(t0, cpu_env, cpu_T0);
} else {
- gen_helper_lsl(t0, cpu_env, cpu_T[0]);
+ gen_helper_lsl(t0, cpu_env, cpu_T0);
}
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
label1 = gen_new_label();
@@ -7405,14 +7439,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
- gen_op_mov_v_reg(ot, cpu_T[0], rm);
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
- cpu_T[0]);
+ cpu_T0);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
- gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg));
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
}
break;
default:
@@ -7442,14 +7476,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
goto illegal_op;
if (b & 2) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
- gen_op_mov_v_reg(ot, cpu_T[0], rm);
- gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
+ gen_op_mov_v_reg(ot, cpu_T0, rm);
+ gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T0);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
- tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
- gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ tcg_gen_ld_tl(cpu_T0, cpu_env, offsetof(CPUX86State, dr[reg]));
+ gen_op_mov_reg_v(ot, rm, cpu_T0);
}
}
break;
@@ -7523,8 +7557,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->mem_index, MO_LEUL);
gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
} else {
- tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
- gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_ld32u_tl(cpu_T0,
+ cpu_env, offsetof(CPUX86State, mxcsr));
+ gen_op_st_v(s, MO_32, cpu_T0, cpu_A0);
}
break;
case 5: /* lfence */
@@ -7583,8 +7618,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
}
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
+ gen_helper_popcnt(cpu_T0, cpu_env, cpu_T0, tcg_const_i32(ot));
+ gen_op_mov_reg_v(ot, reg, cpu_T0);
set_cc_op(s, CC_OP_EFLAGS);
break;
@@ -7760,8 +7795,8 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
printf("ERROR addseg\n");
#endif
- cpu_T[0] = tcg_temp_new();
- cpu_T[1] = tcg_temp_new();
+ cpu_T0 = tcg_temp_new();
+ cpu_T1 = tcg_temp_new();
cpu_A0 = tcg_temp_new();
cpu_tmp0 = tcg_temp_new();
--
1.8.3.1
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 00/60] target-i386 improvements
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
` (59 preceding siblings ...)
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 60/60] target-i386: Deconstruct the cpu_T array Richard Henderson
@ 2013-12-23 20:15 ` Richard Henderson
2013-12-23 22:54 ` Peter Maydell
60 siblings, 1 reply; 75+ messages in thread
From: Richard Henderson @ 2013-12-23 20:15 UTC (permalink / raw)
To: qemu-devel
Ping.
r~
On 11/28/2013 06:59 PM, Richard Henderson wrote:
> Changes v1-v2:
> * Rebased on master, with one of the patches already applied to 1.7.
>
>
> r~
>
>
>
> Richard Henderson (60):
> exec: Delay CPU_LOG_TB_CPU until we actually execute a TB
> target-i386: Push DisasContext into load/store helpers
> target-i386: Stop encoding DisasContext.mem_index
> target-i386: Use new tcg_gen_qemu_ld_* helpers
> target-i386: Use new tcg_gen_qemu_st_* helpers
> target-i386: Replace OT_* constants with MO_* constants
> target-i386: Remove gen_op_ld_T0_A0
> target-i386: Remove gen_op_ldu_T0_A0
> target-i386: Remove gen_op_ld_T1_A0
> target-i386: Remove gen_op_lds_T0_A0
> target-i386: Introduce gen_op_st_rm_T0_A0
> target-i386: Remove gen_op_st_T0_A0
> target-i386: Remove gen_op_st_T1_A0
> target-i386: Fix typo in gen_push_T1
> target-i386: Tidy mov[sz][bw]
> target-i386: Tidy movsl
> target-i386: Remove unused arguments to gen_lea_modrm
> target-i386: Use MO_BE for movbe
> target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32
> target-i386: Tidy load + truncate
> target-i386: Tidy extend + store
> target-i386: Tidy extend + move
> target-i386: Remove gen_op_movl_T0_0
> target-i386: Remove gen_op_movl_T0_im*
> target-i386: Remove gen_op_movl_T0_im*
> target-i386: Remove gen_op_mov*_A0_im
> target-i386: Remove gen_movtl_T*_im
> target-i386: Remove gen_op_andl_T0_ffff
> target-i386: Remove gen_op_andl_T0_im
> target-i386: Remove gen_op_movl_T0_T1
> target-i386: Remove gen_op_andl_A0_ffff
> target-i386: Use TCGMemOp for 'ot' variables
> target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp
> target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp
> target-i386: Change aflag to TCGMemOp
> target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp
> target-i386: Change dflag to TCGMemOp
> target-i386: Tidy addr16 code in gen_lea_modrm
> target-i386: Combine gen_push_T* into gen_push_v
> target_i386: Clean up gen_pop_T0
> target-i386: Create gen_lea_v_seg
> target-i386: Use gen_lea_v_seg in gen_lea_modrm
> target-i386: Use gen_lea_v_seg in stack subroutines
> target-i386: Tidy cpu_regs initialization
> target-i386: Access segs via TCG registers
> target-i386: Use gen_lea_v_seg in pusha/popa
> target-i386: Rewrite gen_enter inline
> target-i386: Introduce mo_stacksize
> target-i386: Rewrite leave
> target-i386: Remove gen_op_mov_reg_T0
> target-i386: Remove gen_op_mov_reg_T1
> target-i386: Remove gen_op_addl_T0_T1
> target-i386: Remove gen_op_mov_TN_reg
> target-i386: Remove gen_op_mov_reg_A0
> target-i386: Remove gen_op_movl_A0_reg
> target-i386: Tidy gen_add_A0_im
> target-i386: Tidy some size computation
> target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v
> target-i386: Tidy ljmp
> target-i386: Deconstruct the cpu_T array
>
> cpu-exec.c | 36 +-
> target-i386/helper.h | 4 -
> target-i386/seg_helper.c | 68 -
> target-i386/translate.c | 3748 ++++++++++++++++++++--------------------------
> 4 files changed, 1623 insertions(+), 2233 deletions(-)
>
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [Qemu-devel] [PATCH v2 00/60] target-i386 improvements
2013-12-23 20:15 ` [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
@ 2013-12-23 22:54 ` Peter Maydell
2013-12-26 19:03 ` Peter Maydell
0 siblings, 1 reply; 75+ messages in thread
From: Peter Maydell @ 2013-12-23 22:54 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 23 December 2013 20:15, Richard Henderson <rth@twiddle.net> wrote:
> Ping.
I made it through as far as patch 38, but really I think this
series is just way too big to review as a single set. There
doesn't seem to be any particularly significant reason for
it to be a single set either. I'll try to work through the
remaining 23 patches later this week, but for future stuff
I'd definitely appreciate more but shorter patch series..
I noticed a few checkpatch warnings (mostly missing
braces, spaces at end of line, overlong lines), generally
where you're touching code that's already noncompliant.
You might like to go through and fix those.
A note on these MO_ op values: it's kinda confusing that
sometimes we use 8/16/32/64 and sometimes BWLQ
(particularly obvious in patches that eg switch from MO_8
&c to MO_SB &c). Personally I'd rather we dropped
the BWLQ versions entirely in favour of _8/_16/_32/_64.
"word" in particular is horrifically ambiguous -- my default
assumption is that "word" means "32 bits", but for QEMU
it's 16. This is just a general observation, not a request
for a change in any of these patches, though.
The patch removing gen_op_movl_T1_im says "T0" in
the subject.
Otherwise, patches 1 to 38
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/60] target-i386 improvements
2013-12-23 22:54 ` Peter Maydell
@ 2013-12-26 19:03 ` Peter Maydell
0 siblings, 0 replies; 75+ messages in thread
From: Peter Maydell @ 2013-12-26 19:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 23 December 2013 22:54, Peter Maydell <peter.maydell@linaro.org> wrote:
> Otherwise, patches 1 to 38
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Patches 39, 40, 44, 45, 50..55, 57..60 also
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Patch 56 I have a query on. Patches 41..43 and 46..49
all involve the lea_v function, regarding which see my comments
on patch 41.
thanks
-- PMM
^ permalink raw reply [flat|nested] 75+ messages in thread