From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v2 03/60] target-i386: Stop encoding DisasContext.mem_index
Date: Fri, 29 Nov 2013 15:59:50 +1300 [thread overview]
Message-ID: <1385694047-6116-4-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net>
Now that we don't combine mem_index with operand size info,
we don't need to encode it. Which tidies many places that
access it.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-i386/translate.c | 67 ++++++++++++++++++-------------------------------
1 file changed, 25 insertions(+), 42 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8c5c16b..40e4826 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -586,7 +586,7 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
@@ -603,7 +603,7 @@ static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_ld8u(t0, a0, mem_index);
@@ -642,7 +642,7 @@ static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
switch(idx & 3) {
case OT_BYTE:
tcg_gen_qemu_st8(t0, a0, mem_index);
@@ -2848,21 +2848,19 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
}
static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
}
static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -2872,7 +2870,7 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
static inline void gen_sto_env_A0(DisasContext *s, int offset)
{
- int mem_index = (s->mem_index >> 2) - 1;
+ int mem_index = s->mem_index;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
@@ -3907,15 +3905,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
offsetof(XMMReg, XMM_L(0)));
break;
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
- tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
offsetof(XMMReg, XMM_W(0)));
break;
@@ -4375,8 +4371,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st8(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x15: /* pextrw */
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
@@ -4384,8 +4379,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st16(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x16:
if (ot == OT_LONG) { /* pextrd */
@@ -4396,8 +4390,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
} else { /* pextrq */
#ifdef TARGET_X86_64
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
@@ -4407,7 +4400,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
else
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ s->mem_index);
#else
goto illegal_op;
#endif
@@ -4419,15 +4412,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_reg_T0(ot, rm);
else
- tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
break;
case 0x20: /* pinsrb */
if (mod == 3)
gen_op_mov_TN_reg(OT_LONG, 0, rm);
else
- tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, s->mem_index);
tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
break;
@@ -4437,8 +4428,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
offsetof(CPUX86State,xmm_regs[rm]
.XMM_L((val >> 6) & 3)));
} else {
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
}
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
@@ -4466,8 +4456,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_v_reg(ot, cpu_tmp0, rm);
else
- tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,
@@ -4478,7 +4467,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
else
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ s->mem_index);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1)));
@@ -6072,8 +6061,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6111,8 +6099,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
break;
case 2:
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
break;
case 3:
@@ -6133,8 +6120,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
break;
case 3:
default:
@@ -6159,8 +6145,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
break;
case 2:
gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
break;
case 3:
default:
@@ -6232,14 +6217,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
gen_helper_fpop(cpu_env);
break;
case 0x3d: /* fildll */
- tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
break;
case 0x3f: /* fistpll */
gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
- tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
- (s->mem_index >> 2) - 1);
+ tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
gen_helper_fpop(cpu_env);
break;
default:
@@ -8320,7 +8303,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
/* select memory access functions */
dc->mem_index = 0;
if (flags & HF_SOFTMMU_MASK) {
- dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
+ dc->mem_index = cpu_mmu_index(env);
}
dc->cpuid_features = env->features[FEAT_1_EDX];
dc->cpuid_ext_features = env->features[FEAT_1_ECX];
--
1.8.3.1
next prev parent reply other threads:[~2013-11-29 3:01 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-29 2:59 [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 01/60] exec: Delay CPU_LOG_TB_CPU until we actually execute a TB Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 02/60] target-i386: Push DisasContext into load/store helpers Richard Henderson
2013-11-29 2:59 ` Richard Henderson [this message]
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 04/60] target-i386: Use new tcg_gen_qemu_ld_* helpers Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 05/60] target-i386: Use new tcg_gen_qemu_st_* helpers Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 06/60] target-i386: Replace OT_* constants with MO_* constants Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 07/60] target-i386: Remove gen_op_ld_T0_A0 Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 08/60] target-i386: Remove gen_op_ldu_T0_A0 Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 09/60] target-i386: Remove gen_op_ld_T1_A0 Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 10/60] target-i386: Remove gen_op_lds_T0_A0 Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 11/60] target-i386: Introduce gen_op_st_rm_T0_A0 Richard Henderson
2013-11-29 2:59 ` [Qemu-devel] [PATCH v2 12/60] target-i386: Remove gen_op_st_T0_A0 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 13/60] target-i386: Remove gen_op_st_T1_A0 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 14/60] target-i386: Fix typo in gen_push_T1 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 15/60] target-i386: Tidy mov[sz][bw] Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 16/60] target-i386: Tidy movsl Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 17/60] target-i386: Remove unused arguments to gen_lea_modrm Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 18/60] target-i386: Use MO_BE for movbe Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 19/60] target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 20/60] target-i386: Tidy load + truncate Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 21/60] target-i386: Tidy extend + store Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 22/60] target-i386: Tidy extend + move Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 23/60] target-i386: Remove gen_op_movl_T0_0 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 24/60] target-i386: Remove gen_op_movl_T0_im* Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 25/60] " Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 26/60] target-i386: Remove gen_op_mov*_A0_im Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 27/60] target-i386: Remove gen_movtl_T*_im Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 28/60] target-i386: Remove gen_op_andl_T0_ffff Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 29/60] target-i386: Remove gen_op_andl_T0_im Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 30/60] target-i386: Remove gen_op_movl_T0_T1 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 31/60] target-i386: Remove gen_op_andl_A0_ffff Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 32/60] target-i386: Use TCGMemOp for 'ot' variables Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 33/60] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 34/60] target-i386: Change gen_op_j*z_ecx " Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 35/60] target-i386: Change aflag " Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 36/60] target-i386: Change gen_op_mov_reg_A0 size parameter " Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 37/60] target-i386: Change dflag " Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 38/60] target-i386: Tidy addr16 code in gen_lea_modrm Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 39/60] target-i386: Combine gen_push_T* into gen_push_v Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 40/60] target_i386: Clean up gen_pop_T0 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 41/60] target-i386: Create gen_lea_v_seg Richard Henderson
2013-12-26 18:38 ` Peter Maydell
2013-12-26 19:31 ` Richard Henderson
2013-12-26 21:27 ` Peter Maydell
2013-12-26 21:31 ` Peter Maydell
2013-12-27 14:49 ` Richard Henderson
2013-12-27 16:06 ` Peter Maydell
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 42/60] target-i386: Use gen_lea_v_seg in gen_lea_modrm Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 43/60] target-i386: Use gen_lea_v_seg in stack subroutines Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 44/60] target-i386: Tidy cpu_regs initialization Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 45/60] target-i386: Access segs via TCG registers Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 46/60] target-i386: Use gen_lea_v_seg in pusha/popa Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 47/60] target-i386: Rewrite gen_enter inline Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 48/60] target-i386: Introduce mo_stacksize Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 49/60] target-i386: Rewrite leave Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 50/60] target-i386: Remove gen_op_mov_reg_T0 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 51/60] target-i386: Remove gen_op_mov_reg_T1 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 52/60] target-i386: Remove gen_op_addl_T0_T1 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 53/60] target-i386: Remove gen_op_mov_TN_reg Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 54/60] target-i386: Remove gen_op_mov_reg_A0 Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 55/60] target-i386: Remove gen_op_movl_A0_reg Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 56/60] target-i386: Tidy gen_add_A0_im Richard Henderson
2013-12-26 18:58 ` Peter Maydell
2013-12-26 19:10 ` Richard Henderson
2013-12-26 22:34 ` Peter Maydell
2013-12-27 15:17 ` Richard Henderson
2013-12-27 15:32 ` Peter Maydell
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 57/60] target-i386: Tidy some size computation Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 58/60] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 59/60] target-i386: Tidy ljmp Richard Henderson
2013-11-29 3:00 ` [Qemu-devel] [PATCH v2 60/60] target-i386: Deconstruct the cpu_T array Richard Henderson
2013-12-23 20:15 ` [Qemu-devel] [PATCH v2 00/60] target-i386 improvements Richard Henderson
2013-12-23 22:54 ` Peter Maydell
2013-12-26 19:03 ` Peter Maydell
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