From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41360) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEOj-0007nP-Gw for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:05:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmEOd-0003hQ-MB for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:05:41 -0500 Received: from mail-pd0-x22c.google.com ([2607:f8b0:400e:c02::22c]:49696) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEOd-0003hG-FJ for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:05:35 -0500 Received: by mail-pd0-f172.google.com with SMTP id g10so13016793pdj.3 for ; Thu, 28 Nov 2013 19:05:34 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.05.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:05:33 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Fri, 29 Nov 2013 16:00:45 +1300 Message-Id: <1385694047-6116-59-git-send-email-rth@twiddle.net> In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 58/60] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org And make the destination argument explicit. Signed-off-by: Richard Henderson --- target-i386/translate.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 9052907..fcf4c67 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -384,9 +384,9 @@ static void gen_add_A0_im(DisasContext *s, int val) } } -static inline void gen_op_jmp_T0(void) +static inline void gen_op_jmp_v(TCGv dest) { - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)); + tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip)); } static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val) @@ -423,7 +423,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) static inline void gen_jmp_im(target_ulong pc) { tcg_gen_movi_tl(cpu_tmp0, pc); - tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)); + gen_op_jmp_v(cpu_tmp0); } /* Compute SEG:REG into A0. SEG is selected from the override segment @@ -4760,7 +4760,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, next_eip = s->pc - s->cs_base; tcg_gen_movi_tl(cpu_T[1], next_eip); gen_push_v(s, cpu_T[1]); - gen_op_jmp_T0(); + gen_op_jmp_v(cpu_T[0]); gen_eob(s); break; case 3: /* lcall Ev */ @@ -4787,7 +4787,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (dflag == MO_16) { tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); } - gen_op_jmp_T0(); + gen_op_jmp_v(cpu_T[0]); gen_eob(s); break; case 5: /* ljmp Ev */ @@ -4804,7 +4804,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_op_movl_seg_T0_vm(R_CS); tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); - gen_op_jmp_T0(); + gen_op_jmp_v(cpu_T[0]); } gen_eob(s); break; @@ -6187,14 +6187,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = gen_pop_T0(s); gen_stack_update(s, val + (1 << ot)); /* Note that gen_pop_T0 uses a zero-extending load. */ - gen_op_jmp_T0(); + gen_op_jmp_v(cpu_T[0]); gen_eob(s); break; case 0xc3: /* ret */ ot = gen_pop_T0(s); gen_pop_update(s, ot); /* Note that gen_pop_T0 uses a zero-extending load. */ - gen_op_jmp_T0(); + gen_op_jmp_v(cpu_T[0]); gen_eob(s); break; case 0xca: /* lret im */ @@ -6212,7 +6212,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0); /* NOTE: keeping EIP updated is not a problem in case of exception */ - gen_op_jmp_T0(); + gen_op_jmp_v(cpu_T[0]); /* pop selector */ gen_add_A0_im(s, 1 << dflag); gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0); -- 1.8.3.1