From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39948) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEKy-0001re-W9 for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:01:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmEKt-000224-1t for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:01:48 -0500 Received: from mail-pb0-x234.google.com ([2607:f8b0:400e:c01::234]:57061) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEKs-00021f-Rj for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:01:42 -0500 Received: by mail-pb0-f52.google.com with SMTP id uo5so13608015pbc.11 for ; Thu, 28 Nov 2013 19:01:41 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.01.39 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:01:41 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Fri, 29 Nov 2013 15:59:55 +1300 Message-Id: <1385694047-6116-9-git-send-email-rth@twiddle.net> In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 08/60] target-i386: Remove gen_op_ldu_T0_A0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Propagate its definition into all users. Signed-off-by: Richard Henderson --- target-i386/translate.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 8e231b3..c64203e 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -586,11 +586,6 @@ static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0) tcg_gen_qemu_ld_tl(t0, a0, s->mem_index, idx | MO_LE); } -static inline void gen_op_ldu_T0_A0(DisasContext *s, int idx) -{ - gen_op_ld_v(s, idx, cpu_T[0], cpu_A0); -} - static inline void gen_op_ld_T1_A0(DisasContext *s, int idx) { gen_op_ld_v(s, idx, cpu_T[1], cpu_A0); @@ -5172,7 +5167,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 3: /* lcall Ev */ gen_op_ld_T1_A0(s, ot); gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); - gen_op_ldu_T0_A0(s, MO_16); + gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); do_lcall: if (s->pe && !s->vm86) { gen_update_cc_op(s); @@ -5198,7 +5193,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 5: /* ljmp Ev */ gen_op_ld_T1_A0(s, ot); gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); - gen_op_ldu_T0_A0(s, MO_16); + gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); do_ljmp: if (s->pe && !s->vm86) { gen_update_cc_op(s); @@ -5711,7 +5706,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (b & 8) { gen_op_lds_T0_A0(s, ot); } else { - gen_op_ldu_T0_A0(s, ot); + gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); } gen_op_mov_reg_T0(d_ot, reg); } @@ -5790,7 +5785,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); } gen_add_A0_ds_seg(s); - gen_op_ldu_T0_A0(s, MO_8); + gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0); gen_op_mov_reg_T0(MO_8, R_EAX); break; case 0xb0 ... 0xb7: /* mov R, Ib */ @@ -5881,7 +5876,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_ld_T1_A0(s, ot); gen_add_A0_im(s, 1 << (ot - MO_16 + 1)); /* load the segment first to handle exceptions properly */ - gen_op_ldu_T0_A0(s, MO_16); + gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0); gen_movl_seg_T0(s, op, pc_start - s->cs_base); /* then put the data */ gen_op_mov_reg_T1(ot, reg); -- 1.8.3.1