From: Will Newton <will.newton@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v7 1/6] target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
Date: Mon, 2 Dec 2013 20:12:52 +0000 [thread overview]
Message-ID: <1386015177-6621-2-git-send-email-will.newton@linaro.org> (raw)
In-Reply-To: <1386015177-6621-1-git-send-email-will.newton@linaro.org>
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
---
target-arm/translate.c | 32 +++++++++++++++++++++++++++-----
1 file changed, 27 insertions(+), 5 deletions(-)
Changes in v7:
- Fix comment style
- Fix brace style
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5f003e7..f63e89d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2636,6 +2636,14 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
&& rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
return 1;
}
+
+ if (extract32(insn, 28, 4) == 0xf) {
+ /* Encodings with T=1 (Thumb) or unconditional (ARM):
+ * only used in v8 and above.
+ */
+ return 1;
+ }
+
dp = ((insn & 0xf00) == 0xb00);
switch ((insn >> 24) & 0xf) {
case 0xe:
@@ -6296,9 +6304,6 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
return disas_dsp_insn(env, s, insn);
}
return 1;
- case 10:
- case 11:
- return disas_vfp_insn (env, s, insn);
default:
break;
}
@@ -6753,6 +6758,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
goto illegal_op;
return;
}
+ if ((insn & 0x0f000e10) == 0x0e000a00) {
+ /* VFP. */
+ if (disas_vfp_insn(env, s, insn)) {
+ goto illegal_op;
+ }
+ return;
+ }
if (((insn & 0x0f30f000) == 0x0510f000) ||
((insn & 0x0f30f010) == 0x0710f000)) {
if ((insn & (1 << 22)) == 0) {
@@ -8033,9 +8045,15 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
case 0xc:
case 0xd:
case 0xe:
- /* Coprocessor. */
- if (disas_coproc_insn(env, s, insn))
+ if (((insn >> 8) & 0xe) == 10) {
+ /* VFP. */
+ if (disas_vfp_insn(env, s, insn)) {
+ goto illegal_op;
+ }
+ } else if (disas_coproc_insn(env, s, insn)) {
+ /* Coprocessor. */
goto illegal_op;
+ }
break;
case 0xf:
/* swi */
@@ -8765,6 +8783,10 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
if (disas_neon_data_insn(env, s, insn))
goto illegal_op;
+ } else if (((insn >> 8) & 0xe) == 10) {
+ if (disas_vfp_insn(env, s, insn)) {
+ goto illegal_op;
+ }
} else {
if (insn & (1 << 28))
goto illegal_op;
--
1.8.1.4
next prev parent reply other threads:[~2013-12-02 20:13 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-02 20:12 [Qemu-devel] [PATCH v7 0/6] target-arm: Add support for VSEL and VMIN/MAXNM Will Newton
2013-12-02 20:12 ` Will Newton [this message]
2013-12-02 21:57 ` [Qemu-devel] [PATCH v7 1/6] target-arm: Move call to disas_vfp_insn out of disas_coproc_insn Peter Maydell
2013-12-02 20:12 ` [Qemu-devel] [PATCH v7 2/6] target-arm: Implement ARMv8 VSEL instruction Will Newton
2013-12-02 22:16 ` Peter Maydell
2013-12-02 20:12 ` [Qemu-devel] [PATCH v7 3/6] softfloat: Remove unused argument from MINMAX macro Will Newton
2013-12-02 21:12 ` Peter Maydell
2013-12-02 20:12 ` [Qemu-devel] [PATCH v7 4/6] softfloat: Add minNum() and maxNum() functions to softfloat Will Newton
2013-12-02 21:55 ` Peter Maydell
2013-12-02 20:12 ` [Qemu-devel] [PATCH v7 5/6] target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions Will Newton
2013-12-02 21:59 ` Peter Maydell
2013-12-02 20:12 ` [Qemu-devel] [PATCH v7 6/6] target-arm: Implement ARMv8 SIMD " Will Newton
2013-12-02 22:13 ` Peter Maydell
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