[Qemu-devel] [PATCH 00/12] target-arm: A64 decoder, foundation plus branches

[Peter Maydell <peter.maydell@linaro.org>]

Hi; this patchset represents the first bit of output of the work
we've been doing in Linaro to help get the SuSE A64 instruction
emulation upstream. Since code review on the 60-patch set Alex
posted suggested that we should rework the decoder skeleton to more
closely match the ARM ARM documentation, it seemed to me like a good
idea to get this first set of patches out now for review, even though
you can't do very much with just branch instructions. Plus I'm hoping
that a set of dozen-patch mouthfuls will go down more smoothly than
if we drop the whole thing on the list at once :-)

Contents:
 * the new decoder skeleton,
 * gdbstub support for FP insns
 * a patch from me which gives the A64 decoder its own
   gen_intermediate_code_internal() loop for simplicity
 * the branch related patches from Alex's series, inserted into
   the new decoder skeleton

These patches sit on top of the v8 KVM control patchset I posted
last week. You can find a git tree with them here:
 git://git.linaro.org/people/pmaydell/qemu-arm.git a64-first-set
web UI:
 https://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/a64-first-set

I think these patches are ready to commit to mainline [ie they have
passed my personal code review]; further review appreciated.
My plan is to put them into the target-arm queue in these smallish
chunks as they pass review.

I've checked and I believe I have the attributions and signoffs
correct here, but it's easy for them to get accidentally mangled
in the course of rebasing, so please say if I missed one.

(The next set is probably going to be a bunch of integer instructions;
we now have a setup which will let us do some decent testing of these
with risu.)


Alexander Graf (7):
  target-arm: A64: add set_pc cpu method
  target-arm: A64: add stubs for a64 specific helpers
  target-arm: A64: add support for B and BL insns
  target-arm: A64: add support for BR, BLR and RET insns
  target-arm: A64: add support for conditional branches
  target-arm: A64: add support for 'test and branch' imm
  target-arm: A64: add support for compare and branch imm

Claudio Fontana (2):
  target-arm: A64: provide skeleton for a64 insn decoding
  target-arm: A64: expand decoding skeleton for system instructions

Peter Maydell (3):
  target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
  target-arm: A64: provide functions for accessing FPCR and FPSR
  target-arm: Support fp registers in gdb stub

 configure                  |    2 +-
 gdb-xml/aarch64-fpu.xml    |   86 +++++
 target-arm/Makefile.objs   |    2 +-
 target-arm/cpu.h           |   28 ++
 target-arm/cpu64.c         |   11 +
 target-arm/helper-a64.c    |   25 ++
 target-arm/helper-a64.h    |   18 +
 target-arm/helper.c        |   48 ++-
 target-arm/helper.h        |    4 +
 target-arm/translate-a64.c |  877 +++++++++++++++++++++++++++++++++++++++++++-
 target-arm/translate.c     |   76 ++--
 target-arm/translate.h     |   25 +-
 12 files changed, 1141 insertions(+), 61 deletions(-)
 create mode 100644 gdb-xml/aarch64-fpu.xml
 create mode 100644 target-arm/helper-a64.c
 create mode 100644 target-arm/helper-a64.h

-- 
1.7.9.5