From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39500) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnxtX-0004m7-3u for qemu-devel@nongnu.org; Tue, 03 Dec 2013 16:52:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VnxtS-0007pm-A0 for qemu-devel@nongnu.org; Tue, 03 Dec 2013 16:52:38 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:35990) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnxtR-0007nW-WF for qemu-devel@nongnu.org; Tue, 03 Dec 2013 16:52:34 -0500 From: Peter Maydell Date: Tue, 3 Dec 2013 21:51:14 +0000 Message-Id: <1386107477-24165-10-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> References: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 09/12] target-arm: A64: add support for BR, BLR and RET insns List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Alexander Graf , C Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson From: Alexander Graf Implement BR, BLR and RET. This is all of the 'unconditional branch (register)' instruction category except for ERET and DPRS (which are system mode only). Signed-off-by: Alexander Graf [claudio: reimplemented on top of new decoder structure] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 43 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 8535803..48281ff 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -365,10 +365,49 @@ static void disas_exc(DisasContext *s, uint32_t insn) unsupported_encoding(s, insn); } -/* Unconditional branch (register) */ +/* C3.2.7 Unconditional branch (register) + * 31 25 24 21 20 16 15 10 9 5 4 0 + * +---------------+-------+-------+-------+------+-------+ + * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | + * +---------------+-------+-------+-------+------+-------+ + */ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int opc, op2, op3, rn, op4; + + opc = extract32(insn, 21, 4); + op2 = extract32(insn, 16, 5); + op3 = extract32(insn, 10, 6); + rn = extract32(insn, 5, 5); + op4 = extract32(insn, 0, 5); + + if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { + unallocated_encoding(s); + return; + } + + switch (opc) { + case 0: /* BR */ + case 2: /* RET */ + break; + case 1: /* BLR */ + tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); + break; + case 4: /* ERET */ + case 5: /* DRPS */ + if (rn != 0x1f) { + unallocated_encoding(s); + } else { + unsupported_encoding(s, insn); + } + return; + default: + unallocated_encoding(s); + return; + } + + tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); + s->is_jmp = DISAS_JUMP; } /* C3.2 Branches, exception generating and system instructions */ -- 1.7.9.5