From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoICW-00071y-W0 for qemu-devel@nongnu.org; Wed, 04 Dec 2013 14:33:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VoICU-0000bV-A9 for qemu-devel@nongnu.org; Wed, 04 Dec 2013 14:33:36 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:42979 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoICU-0000ac-46 for qemu-devel@nongnu.org; Wed, 04 Dec 2013 14:33:34 -0500 From: Peter Maydell Date: Wed, 4 Dec 2013 19:33:17 +0000 Message-Id: <1386185609-25505-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 00/12] target-arm: A64 decoder, foundation plus branches List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Alexander Graf , C Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson Round two of the first-chunk of A64 decoder work, updated following code review. Contents: * the new decoder skeleton, * gdbstub support for FP insns * a patch from me which gives the A64 decoder its own gen_intermediate_code_internal() loop for simplicity * the branch related patches from Alex's series, inserted into the new decoder skeleton These patches sit on top of the v8 KVM control patchset I posted last week. You can find a git tree with them here: git://git.linaro.org/people/pmaydell/qemu-arm.git a64-first-set web UI: https://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/a64-first-set Changes v1->v2: * fixed a non-prettified insn pattern format in a comment * flip order of goto_tbs in cond-branch, test&branch, cmp&branch * read_cpu_reg() now returns a (trashable) TCGv_i64 rather than requiring one to be passed in Alexander Graf (7): target-arm: A64: add set_pc cpu method target-arm: A64: add stubs for a64 specific helpers target-arm: A64: add support for B and BL insns target-arm: A64: add support for BR, BLR and RET insns target-arm: A64: add support for conditional branches target-arm: A64: add support for 'test and branch' imm target-arm: A64: add support for compare and branch imm Claudio Fontana (2): target-arm: A64: provide skeleton for a64 insn decoding target-arm: A64: expand decoding skeleton for system instructions Peter Maydell (3): target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() target-arm: A64: provide functions for accessing FPCR and FPSR target-arm: Support fp registers in gdb stub configure | 2 +- gdb-xml/aarch64-fpu.xml | 86 +++++ target-arm/Makefile.objs | 2 +- target-arm/cpu.h | 28 ++ target-arm/cpu64.c | 11 + target-arm/helper-a64.c | 25 ++ target-arm/helper-a64.h | 18 + target-arm/helper.c | 48 ++- target-arm/helper.h | 4 + target-arm/translate-a64.c | 874 +++++++++++++++++++++++++++++++++++++++++++- target-arm/translate.c | 76 ++-- target-arm/translate.h | 25 +- 12 files changed, 1138 insertions(+), 61 deletions(-) create mode 100644 gdb-xml/aarch64-fpu.xml create mode 100644 target-arm/helper-a64.c create mode 100644 target-arm/helper-a64.h -- 1.7.9.5