From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoIZY-0005Fl-MR for qemu-devel@nongnu.org; Wed, 04 Dec 2013 14:57:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VoIZX-0002Id-1s for qemu-devel@nongnu.org; Wed, 04 Dec 2013 14:57:24 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43015) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoIZW-0002HM-RK for qemu-devel@nongnu.org; Wed, 04 Dec 2013 14:57:23 -0500 From: Peter Maydell Date: Wed, 4 Dec 2013 19:33:28 +0000 Message-Id: <1386185609-25505-12-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1386185609-25505-1-git-send-email-peter.maydell@linaro.org> References: <1386185609-25505-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 11/12] target-arm: A64: add support for 'test and branch' imm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Alexander Graf , C Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson From: Alexander Graf This patch adds emulation for the test and branch insns, TBZ and TBNZ. Signed-off-by: Alexander Graf [claudio: adapted for new decoder always compare with 0 remove a TCG temporary ] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index afad874..b79672b 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -215,10 +215,33 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) unsupported_encoding(s, insn); } -/* Test & branch (immediate) */ +/* C3.2.5 Test & branch (immediate) + * 31 30 25 24 23 19 18 5 4 0 + * +----+-------------+----+-------+-------------+------+ + * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | + * +----+-------------+----+-------+-------------+------+ + */ static void disas_test_b_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int bit_pos, op, rt; + uint64_t addr; + int label_match; + TCGv_i64 tcg_cmp; + + bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); + op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ + addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; + rt = extract32(insn, 0, 5); + + tcg_cmp = tcg_temp_new_i64(); + tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); + label_match = gen_new_label(); + tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, + tcg_cmp, 0, label_match); + tcg_temp_free_i64(tcg_cmp); + gen_goto_tb(s, 0, s->pc); + gen_set_label(label_match); + gen_goto_tb(s, 1, addr); } /* C3.2.2 / C5.6.19 Conditional branch (immediate) -- 1.7.9.5