From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48821) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoYE7-0006Tc-Hl for qemu-devel@nongnu.org; Thu, 05 Dec 2013 07:40:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VoYE0-00007t-TA for qemu-devel@nongnu.org; Thu, 05 Dec 2013 07:40:19 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43030) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoYE0-0008Fy-Lp for qemu-devel@nongnu.org; Thu, 05 Dec 2013 07:40:12 -0500 From: Peter Maydell Date: Thu, 5 Dec 2013 12:39:40 +0000 Message-Id: <1386247180-26994-13-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1386247180-26994-1-git-send-email-peter.maydell@linaro.org> References: <1386247180-26994-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v3 12/12] target-arm: A64: add support for compare and branch imm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , C Fontana , Dirk Mueller , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Richard Henderson From: Alexander Graf This patch adds emulation for the compare and branch insns, CBZ and CBNZ. Signed-off-by: Alexander Graf [claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 46 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 213a98a..fdc3ed8 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -202,6 +202,25 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg) } } +/* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 + * representing the register contents. This TCGv is an auto-freed + * temporary so it need not be explicitly freed, and may be modified. + */ +static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) +{ + TCGv_i64 v = new_tmp_a64(s); + if (reg != 31) { + if (sf) { + tcg_gen_mov_i64(v, cpu_X[reg]); + } else { + tcg_gen_ext32u_i64(v, cpu_X[reg]); + } + } else { + tcg_gen_movi_i64(v, 0); + } + return v; +} + /* * the instruction disassembly implemented here matches * the instruction encoding classifications in chapter 3 (C3) @@ -227,10 +246,33 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) gen_goto_tb(s, 0, addr); } -/* Compare & branch (immediate) */ +/* C3.2.1 Compare & branch (immediate) + * 31 30 25 24 23 5 4 0 + * +----+-------------+----+---------------------+--------+ + * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | + * +----+-------------+----+---------------------+--------+ + */ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int sf, op, rt; + uint64_t addr; + int label_match; + TCGv_i64 tcg_cmp; + + sf = extract32(insn, 31, 1); + op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ + rt = extract32(insn, 0, 5); + addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; + + tcg_cmp = read_cpu_reg(s, rt, sf); + label_match = gen_new_label(); + + tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, + tcg_cmp, 0, label_match); + + gen_goto_tb(s, 0, s->pc); + gen_set_label(label_match); + gen_goto_tb(s, 1, addr); } /* C3.2.5 Test & branch (immediate) -- 1.7.9.5