From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: patches@linaro.org, "Michael Matz" <matz@suse.de>,
"C Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v3 02/12] target-arm: A64: add set_pc cpu method
Date: Thu, 5 Dec 2013 12:39:30 +0000 [thread overview]
Message-ID: <1386247180-26994-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1386247180-26994-1-git-send-email-peter.maydell@linaro.org>
From: Alexander Graf <agraf@suse.de>
When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-arm/cpu64.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 3e99c21..04ce879 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -68,11 +68,22 @@ static void aarch64_cpu_finalizefn(Object *obj)
{
}
+static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ /*
+ * TODO: this will need updating for system emulation,
+ * when the core may be in AArch32 mode.
+ */
+ cpu->env.pc = value;
+}
+
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
cc->dump_state = aarch64_cpu_dump_state;
+ cc->set_pc = aarch64_cpu_set_pc;
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
--
1.7.9.5
next prev parent reply other threads:[~2013-12-05 12:40 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-05 12:39 [Qemu-devel] [PATCH v3 00/12] target-arm: A64 decoder, foundation plus branches Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 01/12] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() Peter Maydell
2013-12-05 12:39 ` Peter Maydell [this message]
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 03/12] target-arm: A64: provide functions for accessing FPCR and FPSR Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 04/12] target-arm: Support fp registers in gdb stub Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 05/12] target-arm: A64: add stubs for a64 specific helpers Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 06/12] target-arm: A64: provide skeleton for a64 insn decoding Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 07/12] target-arm: A64: expand decoding skeleton for system instructions Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 08/12] target-arm: A64: add support for B and BL insns Peter Maydell
2013-12-05 19:34 ` Richard Henderson
2013-12-09 13:49 ` Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 09/12] target-arm: A64: add support for BR, BLR and RET insns Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 10/12] target-arm: A64: add support for conditional branches Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 11/12] target-arm: A64: add support for 'test and branch' imm Peter Maydell
2013-12-05 12:39 ` [Qemu-devel] [PATCH v3 12/12] target-arm: A64: add support for compare and branch imm Peter Maydell
2013-12-05 19:37 ` Richard Henderson
2013-12-17 14:45 ` [Qemu-devel] [PATCH v3 00/12] target-arm: A64 decoder, foundation plus branches Peter Maydell
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