From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44671) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VovQk-0006rC-9v for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:26:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VovQi-0004YH-Fh for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:26:54 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43169) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VovQi-0004WM-7m for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:26:52 -0500 From: Peter Maydell Date: Fri, 6 Dec 2013 13:19:00 +0000 Message-Id: <1386335953-28876-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 00/13] target-arm: A64 decoder set 2: misc logic and bit ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Second revision of the second chunk of A64 decoder patches: a grabbag of miscellaneous logic and bit-twiddling operations, plus some other minor stuff like ADR and conditional-select. Changes v1->v2: * added a couple of OPTME comments as suggested by RTH * lowercased stray TRUE/FALSE * in logical (shifted reg), use andc/orc/eqv rather than explicit not, and special case MOV/MVN * improve cond select code as suggested by RTH (but not attempting any grander reworking of arm_gen_test_cc just yet) NB: only patches 1 and 2 still need review :-) Git tree (with v7-cpu-host/mach-virt, v8 kvm control, and A64 set one all underneath these ptaches): git://git.linaro.org/people/pmaydell/qemu-arm.git a64-second-set web UI: https://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/a64-second-set thanks -- PMM Alexander Graf (7): target-arm: A64: add support for logical (shifted register) target-arm: A64: add support for ADR and ADRP target-arm: A64: add support for EXTR target-arm: A64: add support for 2-src data processing and DIV target-arm: A64: add support for 2-src shift reg insns target-arm: A64: add support for 1-src RBIT insn target-arm: A64: add support for logical (immediate) insns Claudio Fontana (6): target-arm: A64: add support for conditional select target-arm: A64: add support for 1-src data processing and CLZ target-arm: A64: add support for 1-src REV insns target-arm: A64: add support for bitfield insns host-utils: add clrsb32/64 - count leading redundant sign bits target-arm: A64: add support for 1-src CLS insn include/qemu/host-utils.h | 32 ++ target-arm/helper-a64.c | 54 +++ target-arm/helper-a64.h | 6 + target-arm/translate-a64.c | 816 ++++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 888 insertions(+), 20 deletions(-) -- 1.7.9.5