From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44610) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VovQi-0006qv-Vg for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:26:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VovQg-0004Wr-Hq for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:26:52 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43169) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VovQg-0004WM-Au for qemu-devel@nongnu.org; Fri, 06 Dec 2013 08:26:50 -0500 From: Peter Maydell Date: Fri, 6 Dec 2013 13:19:04 +0000 Message-Id: <1386335953-28876-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1386335953-28876-1-git-send-email-peter.maydell@linaro.org> References: <1386335953-28876-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 04/13] target-arm: A64: add support for EXTR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson From: Alexander Graf This patch adds emulation support for the EXTR instruction. Signed-off-by: Alexander Graf [claudio: adapted for new decoder, removed a few temporaries, fixed the 32bit bug, added checks for more unallocated cases] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 49 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 90eaf02..5a822a5 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -704,10 +704,55 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) unsupported_encoding(s, insn); } -/* Extract */ +/* C3.4.3 Extract + * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 + * +----+------+-------------+---+----+------+--------+------+------+ + * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | + * +----+------+-------------+---+----+------+--------+------+------+ + */ static void disas_extract(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; + + sf = extract32(insn, 31, 1); + n = extract32(insn, 22, 1); + rm = extract32(insn, 16, 5); + imm = extract32(insn, 10, 6); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + op21 = extract32(insn, 29, 2); + op0 = extract32(insn, 21, 1); + bitsize = sf ? 64 : 32; + + if (sf != n || op21 || op0 || imm >= bitsize) { + unallocated_encoding(s); + } else { + TCGv_i64 tcg_rd, tcg_rm, tcg_rn; + + tcg_rd = cpu_reg(s, rd); + + if (imm) { + /* OPTME: we can special case rm==rn as a rotate */ + tcg_rm = read_cpu_reg(s, rm, sf); + tcg_rn = read_cpu_reg(s, rn, sf); + tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); + tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); + tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); + if (!sf) { + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + } + } else { + /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, + * so an extract from bit 0 is a special case. + */ + if (sf) { + tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); + } else { + tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); + } + } + + } } /* C3.4 Data processing - immediate */ -- 1.7.9.5