From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48223) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VotjM-0007cz-IE for qemu-devel@nongnu.org; Fri, 06 Dec 2013 06:38:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VotjG-0004eD-5B for qemu-devel@nongnu.org; Fri, 06 Dec 2013 06:38:00 -0500 Received: from mga14.intel.com ([143.182.124.37]:38343) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VotjF-0004dw-UA for qemu-devel@nongnu.org; Fri, 06 Dec 2013 06:37:54 -0500 From: Qiaowei Ren Date: Sat, 7 Dec 2013 02:52:55 +0800 Message-Id: <1386355976-11732-2-git-send-email-qiaowei.ren@intel.com> In-Reply-To: <1386355976-11732-1-git-send-email-qiaowei.ren@intel.com> References: <1386355976-11732-1-git-send-email-qiaowei.ren@intel.com> Subject: [Qemu-devel] [PATCH 2/3] X86, mpx: Intel MPX definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , "H. Peter Anvin" , Ingo Molnar , Thomas Gleixner , x86@kernel.org Cc: Liu Jinsong , kvm@vger.kernel.org, Xudong Hao , linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, Qiaowei Ren Signed-off-by: Qiaowei Ren Signed-off-by: Xudong Hao Signed-off-by: Liu Jinsong --- arch/x86/include/asm/cpufeature.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index d3f5c63..6c2738d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -216,6 +216,7 @@ #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ +#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */ #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ @@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32]; #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) -- 1.7.1