From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49939) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vp3DP-0005PH-DZ for qemu-devel@nongnu.org; Fri, 06 Dec 2013 16:45:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vp3DJ-0007hl-Hy for qemu-devel@nongnu.org; Fri, 06 Dec 2013 16:45:39 -0500 Received: from mail-qc0-x22c.google.com ([2607:f8b0:400d:c01::22c]:41994) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vp3DJ-0007hb-EU for qemu-devel@nongnu.org; Fri, 06 Dec 2013 16:45:33 -0500 Received: by mail-qc0-f172.google.com with SMTP id e16so932738qcx.17 for ; Fri, 06 Dec 2013 13:45:32 -0800 (PST) Received: from pebble.com ([202.180.67.114]) by mx.google.com with ESMTPSA id x10sm178438865qas.5.2013.12.06.13.45.29 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Dec 2013 13:45:31 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Sat, 7 Dec 2013 10:44:51 +1300 Message-Id: <1386366292-5340-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 1/2] cputlb: Use memset when flushing entries List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The size of tlb_table is 4k on a 64-bit host. For overwriting memory at this size, cacheline tricks can help. Signed-off-by: Richard Henderson --- cputlb.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/cputlb.c b/cputlb.c index fff0afb..d2da404 100644 --- a/cputlb.c +++ b/cputlb.c @@ -33,13 +33,6 @@ /* statistics */ int tlb_flush_count; -static const CPUTLBEntry s_cputlb_empty_entry = { - .addr_read = -1, - .addr_write = -1, - .addr_code = -1, - .addend = -1, -}; - /* NOTE: * If flush_global is true (the usual case), flush all tlb entries. * If flush_global is false, flush (at least) all tlb entries not @@ -55,7 +48,6 @@ static const CPUTLBEntry s_cputlb_empty_entry = { void tlb_flush(CPUArchState *env, int flush_global) { CPUState *cpu = ENV_GET_CPU(env); - int i; #if defined(DEBUG_TLB) printf("tlb_flush:\n"); @@ -64,14 +56,7 @@ void tlb_flush(CPUArchState *env, int flush_global) links while we are modifying them */ cpu->current_tb = NULL; - for (i = 0; i < CPU_TLB_SIZE; i++) { - int mmu_idx; - - for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; - } - } - + memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); env->tlb_flush_addr = -1; @@ -87,7 +72,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || addr == (tlb_entry->addr_code & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - *tlb_entry = s_cputlb_empty_entry; + memset(tlb_entry, -1, sizeof(*tlb_entry)); } } -- 1.8.3.1