From: Qiaowei Ren <qiaowei.ren@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
x86@kernel.org
Cc: Liu Jinsong <jinsong.liu@intel.com>,
kvm@vger.kernel.org, Xudong Hao <xudong.hao@intel.com>,
linux-kernel@vger.kernel.org, qemu-devel@nongnu.org,
Qiaowei Ren <qiaowei.ren@intel.com>
Subject: [Qemu-devel] [PATCH v2 3/3] X86, mpx: Intel MPX xstate feature definition
Date: Sat, 7 Dec 2013 08:20:58 +0800 [thread overview]
Message-ID: <1386375658-2191-3-git-send-email-qiaowei.ren@intel.com> (raw)
In-Reply-To: <1386375658-2191-1-git-send-email-qiaowei.ren@intel.com>
This patch defines xstate feature and extends struct xsave_hdr_struct
to support Intel MPX.
Signed-off-by: Qiaowei Ren <qiaowei.ren@intel.com>
Signed-off-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
arch/x86/include/asm/processor.h | 12 ++++++++++++
arch/x86/include/asm/xsave.h | 5 ++++-
2 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 987c75e..2fe2e75 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -370,6 +370,15 @@ struct ymmh_struct {
u32 ymmh_space[64];
};
+struct bndregs_struct {
+ u64 bndregs[8];
+} __packed;
+
+struct bndcsr_struct {
+ u64 cfg_reg_u;
+ u64 status_reg;
+} __packed;
+
struct xsave_hdr_struct {
u64 xstate_bv;
u64 reserved1[2];
@@ -380,6 +389,9 @@ struct xsave_struct {
struct i387_fxsave_struct i387;
struct xsave_hdr_struct xsave_hdr;
struct ymmh_struct ymmh;
+ u8 lwp_area[128];
+ struct bndregs_struct bndregs;
+ struct bndcsr_struct bndcsr;
/* new processor state extensions will go here */
} __attribute__ ((packed, aligned (64)));
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 0415cda..7fa8855 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -9,6 +9,8 @@
#define XSTATE_FP 0x1
#define XSTATE_SSE 0x2
#define XSTATE_YMM 0x4
+#define XSTATE_BNDREGS 0x8
+#define XSTATE_BNDCSR 0x10
#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -20,10 +22,11 @@
#define XSAVE_YMM_SIZE 256
#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
+#define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR)
/*
* These are the features that the OS can handle currently.
*/
-#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+#define XCNTXT_MASK (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | XSTATE_EAGER)
#ifdef CONFIG_X86_64
#define REX_PREFIX "0x48, "
--
1.7.1
next prev parent reply other threads:[~2013-12-06 17:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-07 0:20 [Qemu-devel] [PATCH v2 1/3] x86, mpx: add documentation on Intel MPX Qiaowei Ren
2013-12-07 0:20 ` [Qemu-devel] [PATCH v2 2/3] X86, mpx: Intel MPX CPU feature definition Qiaowei Ren
2013-12-07 0:20 ` Qiaowei Ren [this message]
2013-12-06 17:35 ` [Qemu-devel] [PATCH v2 3/3] X86, mpx: Intel MPX xstate " Paolo Bonzini
2013-12-06 17:55 ` H. Peter Anvin
2013-12-06 20:05 ` Liu, Jinsong
2013-12-06 21:33 ` H. Peter Anvin
2013-12-06 22:12 ` Liu, Jinsong
2013-12-07 0:23 ` Ren, Qiaowei
2013-12-07 1:07 ` H. Peter Anvin
2013-12-07 1:16 ` Ren, Qiaowei
2013-12-07 1:19 ` H. Peter Anvin
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