From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Claudio Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops
Date: Mon, 9 Dec 2013 12:37:21 +0000 [thread overview]
Message-ID: <1386592654-362-1-git-send-email-peter.maydell@linaro.org> (raw)
Third revision of the second chunk of A64 decoder patches:
a grabbag of miscellaneous logic and bit-twiddling operations,
plus some other minor stuff like ADR and conditional-select.
Changes v2->v3:
* patch 1/13: added the special case of rd==31 to avoid the
dead temporary across basic blocks
Changes v1->v2:
* added a couple of OPTME comments as suggested by RTH
* lowercased stray TRUE/FALSE
* in logical (shifted reg), use andc/orc/eqv rather than
explicit not, and special case MOV/MVN
* improve cond select code as suggested by RTH (but not
attempting any grander reworking of arm_gen_test_cc just yet)
Git tree (with v7-cpu-host/mach-virt, v8 kvm control,
and A64 set one all underneath these patches):
git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-second-set
[old git url with 'pmaydell' rather than 'peter.maydell also
still works if you have it in your git config already]
web UI:
https://git.linaro.org/people/peter.maydell/qemu-arm.git/shortlog/refs/heads/a64-second-set
thanks
-- PMM
Alexander Graf (7):
target-arm: A64: add support for logical (shifted register)
target-arm: A64: add support for ADR and ADRP
target-arm: A64: add support for EXTR
target-arm: A64: add support for 2-src data processing and DIV
target-arm: A64: add support for 2-src shift reg insns
target-arm: A64: add support for 1-src RBIT insn
target-arm: A64: add support for logical (immediate) insns
Claudio Fontana (6):
target-arm: A64: add support for conditional select
target-arm: A64: add support for 1-src data processing and CLZ
target-arm: A64: add support for 1-src REV insns
target-arm: A64: add support for bitfield insns
host-utils: add clrsb32/64 - count leading redundant sign bits
target-arm: A64: add support for 1-src CLS insn
include/qemu/host-utils.h | 32 ++
target-arm/helper-a64.c | 54 +++
target-arm/helper-a64.h | 6 +
target-arm/translate-a64.c | 824 +++++++++++++++++++++++++++++++++++++++++++--
4 files changed, 896 insertions(+), 20 deletions(-)
--
1.8.5
next reply other threads:[~2013-12-09 12:57 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 12:37 Peter Maydell [this message]
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select Peter Maydell
2013-12-09 17:03 ` Richard Henderson
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 02/13] target-arm: A64: add support for logical (shifted register) Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 03/13] target-arm: A64: add support for ADR and ADRP Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 05/13] target-arm: A64: add support for 2-src data processing and DIV Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 06/13] target-arm: A64: add support for 2-src shift reg insns Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 07/13] target-arm: A64: add support for 1-src data processing and CLZ Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 08/13] target-arm: A64: add support for 1-src RBIT insn Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 09/13] target-arm: A64: add support for 1-src REV insns Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 10/13] target-arm: A64: add support for bitfield insns Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS insn Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 13/13] target-arm: A64: add support for logical (immediate) insns Peter Maydell
2013-12-17 14:45 ` [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops Peter Maydell
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