From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53354) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vq0OW-0007pJ-Oa for qemu-devel@nongnu.org; Mon, 09 Dec 2013 07:57:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vq0OU-00060o-U9 for qemu-devel@nongnu.org; Mon, 09 Dec 2013 07:57:04 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43253) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vq0OU-00060j-N3 for qemu-devel@nongnu.org; Mon, 09 Dec 2013 07:57:02 -0500 From: Peter Maydell Date: Mon, 9 Dec 2013 12:37:21 +0000 Message-Id: <1386592654-362-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Third revision of the second chunk of A64 decoder patches: a grabbag of miscellaneous logic and bit-twiddling operations, plus some other minor stuff like ADR and conditional-select. Changes v2->v3: * patch 1/13: added the special case of rd==31 to avoid the dead temporary across basic blocks Changes v1->v2: * added a couple of OPTME comments as suggested by RTH * lowercased stray TRUE/FALSE * in logical (shifted reg), use andc/orc/eqv rather than explicit not, and special case MOV/MVN * improve cond select code as suggested by RTH (but not attempting any grander reworking of arm_gen_test_cc just yet) Git tree (with v7-cpu-host/mach-virt, v8 kvm control, and A64 set one all underneath these patches): git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-second-set [old git url with 'pmaydell' rather than 'peter.maydell also still works if you have it in your git config already] web UI: https://git.linaro.org/people/peter.maydell/qemu-arm.git/shortlog/refs/heads/a64-second-set thanks -- PMM Alexander Graf (7): target-arm: A64: add support for logical (shifted register) target-arm: A64: add support for ADR and ADRP target-arm: A64: add support for EXTR target-arm: A64: add support for 2-src data processing and DIV target-arm: A64: add support for 2-src shift reg insns target-arm: A64: add support for 1-src RBIT insn target-arm: A64: add support for logical (immediate) insns Claudio Fontana (6): target-arm: A64: add support for conditional select target-arm: A64: add support for 1-src data processing and CLZ target-arm: A64: add support for 1-src REV insns target-arm: A64: add support for bitfield insns host-utils: add clrsb32/64 - count leading redundant sign bits target-arm: A64: add support for 1-src CLS insn include/qemu/host-utils.h | 32 ++ target-arm/helper-a64.c | 54 +++ target-arm/helper-a64.h | 6 + target-arm/translate-a64.c | 824 +++++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 896 insertions(+), 20 deletions(-) -- 1.8.5