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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: patches@linaro.org, "Michael Matz" <matz@suse.de>,
	"Claudio Fontana" <claudio.fontana@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	kvmarm@lists.cs.columbia.edu,
	"Christoffer Dall" <christoffer.dall@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v3 10/13] target-arm: A64: add support for bitfield insns
Date: Mon,  9 Dec 2013 12:37:31 +0000	[thread overview]
Message-ID: <1386592654-362-11-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1386592654-362-1-git-send-email-peter.maydell@linaro.org>

From: Claudio Fontana <claudio.fontana@linaro.org>

This patch implements the C3.4.2 Bitfield instructions:
SBFM, BFM, UBFM.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 0663e4c..045a25e 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -698,10 +698,62 @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
     unsupported_encoding(s, insn);
 }
 
-/* Bitfield */
+/* C3.4.2 Bitfield
+ *   31  30 29 28         23 22  21  16 15  10 9    5 4    0
+ * +----+-----+-------------+---+------+------+------+------+
+ * | sf | opc | 1 0 0 1 1 0 | N | immr | imms |  Rn  |  Rd  |
+ * +----+-----+-------------+---+------+------+------+------+
+ */
 static void disas_bitfield(DisasContext *s, uint32_t insn)
 {
-    unsupported_encoding(s, insn);
+    unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
+    TCGv_i64 tcg_rd, tcg_tmp;
+
+    sf = extract32(insn, 31, 1);
+    opc = extract32(insn, 29, 2);
+    n = extract32(insn, 22, 1);
+    ri = extract32(insn, 16, 6);
+    si = extract32(insn, 10, 6);
+    rn = extract32(insn, 5, 5);
+    rd = extract32(insn, 0, 5);
+    bitsize = sf ? 64 : 32;
+
+    if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    tcg_rd = cpu_reg(s, rd);
+    tcg_tmp = read_cpu_reg(s, rn, sf);
+
+    /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
+
+    if (opc != 1) { /* SBFM or UBFM */
+        tcg_gen_movi_i64(tcg_rd, 0);
+    }
+
+    /* do the bit move operation */
+    if (si >= ri) {
+        /* Wd<s-r:0> = Wn<s:r> */
+        tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
+        pos = 0;
+        len = (si - ri) + 1;
+    } else {
+        /* Wd<32+s-r,32-r> = Wn<s:0> */
+        pos = bitsize - ri;
+        len = si + 1;
+    }
+
+    tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
+
+    if (opc == 0) { /* SBFM - sign extend the destination field */
+        tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
+        tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
+    }
+
+    if (!sf) { /* zero extend final result */
+        tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+    }
 }
 
 /* C3.4.3 Extract
-- 
1.8.5

  parent reply	other threads:[~2013-12-09 12:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-09 12:37 [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select Peter Maydell
2013-12-09 17:03   ` Richard Henderson
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 02/13] target-arm: A64: add support for logical (shifted register) Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 03/13] target-arm: A64: add support for ADR and ADRP Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 05/13] target-arm: A64: add support for 2-src data processing and DIV Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 06/13] target-arm: A64: add support for 2-src shift reg insns Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 07/13] target-arm: A64: add support for 1-src data processing and CLZ Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 08/13] target-arm: A64: add support for 1-src RBIT insn Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 09/13] target-arm: A64: add support for 1-src REV insns Peter Maydell
2013-12-09 12:37 ` Peter Maydell [this message]
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS insn Peter Maydell
2013-12-09 12:37 ` [Qemu-devel] [PATCH v3 13/13] target-arm: A64: add support for logical (immediate) insns Peter Maydell
2013-12-17 14:45 ` [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops Peter Maydell

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