From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vq05m-0003cR-IP for qemu-devel@nongnu.org; Mon, 09 Dec 2013 07:37:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vq05k-0000B9-Eq for qemu-devel@nongnu.org; Mon, 09 Dec 2013 07:37:42 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43237) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vq05k-0000B4-7E for qemu-devel@nongnu.org; Mon, 09 Dec 2013 07:37:40 -0500 From: Peter Maydell Date: Mon, 9 Dec 2013 12:37:31 +0000 Message-Id: <1386592654-362-11-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1386592654-362-1-git-send-email-peter.maydell@linaro.org> References: <1386592654-362-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v3 10/13] target-arm: A64: add support for bitfield insns List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson From: Claudio Fontana This patch implements the C3.4.2 Bitfield instructions: SBFM, BFM, UBFM. Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 0663e4c..045a25e 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -698,10 +698,62 @@ static void disas_movw_imm(DisasContext *s, uint32_t insn) unsupported_encoding(s, insn); } -/* Bitfield */ +/* C3.4.2 Bitfield + * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 + * +----+-----+-------------+---+------+------+------+------+ + * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | + * +----+-----+-------------+---+------+------+------+------+ + */ static void disas_bitfield(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; + TCGv_i64 tcg_rd, tcg_tmp; + + sf = extract32(insn, 31, 1); + opc = extract32(insn, 29, 2); + n = extract32(insn, 22, 1); + ri = extract32(insn, 16, 6); + si = extract32(insn, 10, 6); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + bitsize = sf ? 64 : 32; + + if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { + unallocated_encoding(s); + return; + } + + tcg_rd = cpu_reg(s, rd); + tcg_tmp = read_cpu_reg(s, rn, sf); + + /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */ + + if (opc != 1) { /* SBFM or UBFM */ + tcg_gen_movi_i64(tcg_rd, 0); + } + + /* do the bit move operation */ + if (si >= ri) { + /* Wd = Wn */ + tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); + pos = 0; + len = (si - ri) + 1; + } else { + /* Wd<32+s-r,32-r> = Wn */ + pos = bitsize - ri; + len = si + 1; + } + + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); + + if (opc == 0) { /* SBFM - sign extend the destination field */ + tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len)); + tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len)); + } + + if (!sf) { /* zero extend final result */ + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + } } /* C3.4.3 Extract -- 1.8.5