From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-ppc@nongnu.org
Subject: [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions
Date: Mon, 9 Dec 2013 09:47:02 -0600 [thread overview]
Message-ID: <1386604035-2507-6-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1386604035-2507-1-git-send-email-tommusta@gmail.com>
This patch addes the Signed and Unsigned Divide Word Extended
instructions which were introduced in Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 74 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b274a15..afab0cf 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -984,6 +984,76 @@ GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
/* divw divw. divwo divwo. */
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
+
+#define GEN_DIVWE(op, signed, compute_ov) \
+static void gen_##op(DisasContext *ctx) \
+{ \
+ /* Need to use local temps because of the branches */ \
+ TCGv ra = tcg_temp_local_new(); \
+ TCGv rb = tcg_temp_local_new(); \
+ int lbl_ov = gen_new_label(); \
+ int lbl_rc = gen_new_label(); \
+ \
+ \
+ if (signed) { \
+ /* divide by zero ? */ \
+ tcg_gen_ext32s_i64(rb, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, rb, 0, lbl_ov); \
+ tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
+ /* check for MIN div -1 */ \
+ int l3 = gen_new_label(); \
+ tcg_gen_brcondi_i64(TCG_COND_NE, rb, -1l, l3); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, ra, INT64_MIN, lbl_ov); \
+ gen_set_label(l3); \
+ tcg_gen_div_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \
+ /* does the result fit in 32 bits? */ \
+ tcg_gen_brcondi_i64(TCG_COND_LT, cpu_gpr[rD(ctx->opcode)], INT32_MIN, \
+ lbl_ov); \
+ tcg_gen_brcondi_i64(TCG_COND_GT, cpu_gpr[rD(ctx->opcode)], INT32_MAX, \
+ lbl_ov); \
+ } else { /* unsigned */ \
+ /* divide by zero ? */ \
+ tcg_gen_ext32u_i64(rb, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, rb, 0, lbl_ov); \
+ /* is ra[32:63] > rb[32:63] ? */ \
+ tcg_gen_ext32u_i64(ra, cpu_gpr[rA(ctx->opcode)]); \
+ tcg_gen_brcond_i64(TCG_COND_GTU, ra, rb, lbl_ov); \
+ tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
+ tcg_gen_divu_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \
+ } \
+ \
+ if (compute_ov) { \
+ tcg_gen_movi_tl(cpu_ov, 0); \
+ } \
+ tcg_gen_br(lbl_rc); \
+ \
+ gen_set_label(lbl_ov); /* overflow handling */ \
+ \
+ if (signed) { \
+ tcg_gen_sari_i64(cpu_gpr[rD(ctx->opcode)], ra, 63); \
+ } else { \
+ tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], 0); \
+ } \
+ \
+ if (compute_ov) { \
+ tcg_gen_movi_tl(cpu_ov, 1); \
+ tcg_gen_movi_tl(cpu_so, 1); \
+ } \
+ \
+ gen_set_label(lbl_rc); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
+ } \
+ \
+ tcg_temp_free(ra); \
+ tcg_temp_free(rb); \
+}
+
+GEN_DIVWE(divweu, 0, 0);
+GEN_DIVWE(divweuo, 0, 1);
+GEN_DIVWE(divwe, 1, 0);
+GEN_DIVWE(divweo, 1, 1);
+
#if defined(TARGET_PPC64)
static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
@@ -9603,6 +9673,10 @@ GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
+GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0x00000000, PPC_NONE, PPC2_ISA206),
#if defined(TARGET_PPC64)
#undef GEN_INT_ARITH_DIVD
--
1.7.1
next prev parent reply other threads:[~2013-12-09 15:48 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
2013-12-09 15:46 ` [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
2013-12-18 22:02 ` Scott Wood
2013-12-18 22:09 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-12-18 22:11 ` Scott Wood
2013-12-18 22:37 ` Alexander Graf
2013-12-19 15:35 ` Tom Musta
2013-12-19 17:17 ` Scott Wood
2013-12-09 15:46 ` [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
2013-12-10 0:01 ` Richard Henderson
2013-12-10 17:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
2013-12-10 0:05 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions Tom Musta
2013-12-09 15:47 ` Tom Musta [this message]
2013-12-10 0:26 ` [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Richard Henderson
2013-12-10 17:58 ` Tom Musta
2013-12-10 18:30 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
2013-12-10 0:31 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
2013-12-10 0:41 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 Tom Musta
2013-12-13 0:13 ` Peter Maydell
2013-12-16 15:20 ` Tom Musta
2013-12-16 15:24 ` Peter Maydell
2013-12-16 15:26 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 11/18] softfloat: Fix float64_to_uint32 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 14/18] target-ppc: Fix and enable fri[mnpz] Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 16/18] target-ppc: Add ISA 2.06 ftsqrt Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 17/18] target-ppc: Enable frsqrtes on Power7 and Power8 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 18/18] target-ppc: Add ISA2.06 lfiwzx Instruction Tom Musta
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