From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-ppc@nongnu.org
Subject: [Qemu-devel] [PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions
Date: Mon, 9 Dec 2013 09:47:05 -0600 [thread overview]
Message-ID: <1386604035-2507-9-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1386604035-2507-1-git-send-email-tommusta@gmail.com>
This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:
- Floating Convert to Integer Word Unsigned (fctiwu)
- Floating Convert to Integer Word Unsigned with Round Toward
Zero (fctiwuz)
- Floating Convert to Integer Doubleword Unsigned (fctidu)
- Floating Convert to Integer Doubleword Unsigned with Round
Toward Zero (fctiduz)
A common macro is developed to eliminate repetitive code. Existing instructions
are also re-implemented to use this macro (fctiw, fctiwz, fctid, fctidz), thus
eliminating copy/paste code.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/fpu_helper.c | 122 +++++++++++++----------------------------------
target-ppc/helper.h | 4 ++
target-ppc/translate.c | 12 +++++
3 files changed, 50 insertions(+), 88 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 5bc8659..4c3cca7 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -600,55 +600,41 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
return farg1.ll;
}
-/* fctiw - fctiw. */
-uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
-
- farg.ll = arg;
-
- if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
- } else {
- farg.ll = float64_to_int32(farg.d, &env->fp_status);
- /* XXX: higher bits are not supposed to be significant.
- * to make tests easier, return the same as a real PowerPC 750
- */
- farg.ll |= 0xFFF80000ULL << 32;
- }
- return farg.ll;
-}
-
-/* fctiwz - fctiwz. */
-uint64_t helper_fctiwz(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
- farg.ll = arg;
+#define FPU_FCTI(op, cvt, nanval) \
+uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
+{ \
+ CPU_DoubleU farg; \
+ \
+ farg.ll = arg; \
+ farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \
+ \
+ if (unlikely(env->fp_status.float_exception_flags)) { \
+ if (float64_is_any_nan(arg)) { \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
+ if (float64_is_signaling_nan(arg)) { \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
+ } \
+ farg.ll = nanval; \
+ } else if (env->fp_status.float_exception_flags & \
+ float_flag_invalid) { \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
+ } \
+ helper_float_check_status(env); \
+ } \
+ return farg.ll; \
+ }
- if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
- } else {
- farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
- /* XXX: higher bits are not supposed to be significant.
- * to make tests easier, return the same as a real PowerPC 750
- */
- farg.ll |= 0xFFF80000ULL << 32;
- }
- return farg.ll;
-}
+FPU_FCTI(fctiw, int32, 0x80000000)
+FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000)
+FPU_FCTI(fctiwu, uint32, 0x00000000)
+FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000)
+#if defined(TARGET_PPC64)
+FPU_FCTI(fctid, int64, 0x8000000000000000)
+FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000)
+FPU_FCTI(fctidu, uint64, 0x0000000000000000)
+FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000)
+#endif
#if defined(TARGET_PPC64)
/* fcfid - fcfid. */
@@ -660,47 +646,7 @@ uint64_t helper_fcfid(CPUPPCState *env, uint64_t arg)
return farg.ll;
}
-/* fctid - fctid. */
-uint64_t helper_fctid(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
- farg.ll = arg;
-
- if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
- } else {
- farg.ll = float64_to_int64(farg.d, &env->fp_status);
- }
- return farg.ll;
-}
-
-/* fctidz - fctidz. */
-uint64_t helper_fctidz(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
-
- farg.ll = arg;
-
- if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity conversion */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
- } else {
- farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
- }
- return farg.ll;
-}
#endif
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4359009..4518da0 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -64,11 +64,15 @@ DEF_HELPER_4(fcmpo, void, env, i64, i64, i32)
DEF_HELPER_4(fcmpu, void, env, i64, i64, i32)
DEF_HELPER_2(fctiw, i64, env, i64)
+DEF_HELPER_2(fctiwu, i64, env, i64)
DEF_HELPER_2(fctiwz, i64, env, i64)
+DEF_HELPER_2(fctiwuz, i64, env, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_2(fcfid, i64, env, i64)
DEF_HELPER_2(fctid, i64, env, i64)
+DEF_HELPER_2(fctidu, i64, env, i64)
DEF_HELPER_2(fctidz, i64, env, i64)
+DEF_HELPER_2(fctiduz, i64, env, i64)
#endif
DEF_HELPER_2(frsp, i64, env, i64)
DEF_HELPER_2(frin, i64, env, i64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 29c5dc1..55da80a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2267,8 +2267,12 @@ GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
/*** Floating-Point round & convert ***/
/* fctiw */
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
+/* fctiwu */
+GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_ISA206);
/* fctiwz */
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
+/* fctiwuz */
+GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_ISA206);
/* frsp */
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
#if defined(TARGET_PPC64)
@@ -2276,8 +2280,12 @@ GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
/* fctid */
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
+/* fctidu */
+GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_ISA206);
/* fctidz */
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
+/* fctidu */
+GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_ISA206);
#endif
/* frin */
@@ -9793,12 +9801,16 @@ GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
+GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
+GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
#if defined(TARGET_PPC64)
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
+GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
+GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
#endif
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
--
1.7.1
next prev parent reply other threads:[~2013-12-09 15:48 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 15:46 [Qemu-devel] [PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
2013-12-09 15:46 ` [Qemu-devel] [PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
2013-12-18 22:02 ` Scott Wood
2013-12-18 22:09 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-12-18 22:11 ` Scott Wood
2013-12-18 22:37 ` Alexander Graf
2013-12-19 15:35 ` Tom Musta
2013-12-19 17:17 ` Scott Wood
2013-12-09 15:46 ` [Qemu-devel] [PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
2013-12-10 0:01 ` Richard Henderson
2013-12-10 17:47 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
2013-12-10 0:05 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Tom Musta
2013-12-10 0:26 ` Richard Henderson
2013-12-10 17:58 ` Tom Musta
2013-12-10 18:30 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
2013-12-10 0:31 ` Richard Henderson
2013-12-09 15:47 ` [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
2013-12-10 0:41 ` Richard Henderson
2013-12-09 15:47 ` Tom Musta [this message]
2013-12-09 15:47 ` [Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 Tom Musta
2013-12-13 0:13 ` Peter Maydell
2013-12-16 15:20 ` Tom Musta
2013-12-16 15:24 ` Peter Maydell
2013-12-16 15:26 ` Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 11/18] softfloat: Fix float64_to_uint32 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 14/18] target-ppc: Fix and enable fri[mnpz] Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 16/18] target-ppc: Add ISA 2.06 ftsqrt Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 17/18] target-ppc: Enable frsqrtes on Power7 and Power8 Tom Musta
2013-12-09 15:47 ` [Qemu-devel] [PATCH 18/18] target-ppc: Add ISA2.06 lfiwzx Instruction Tom Musta
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